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參數(shù)資料
| 型號： | CS4299-JQZR |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 28/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AC 97 W/SRC 48-LQFP |
| 標準包裝： | 2,000 |
| 系列： | SoundFusion™ |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 18 b，20 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調變： | 是 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 85 / 87 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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CS4299
34
5.2
Powerdown Controls
The
Powerdown
Control/Status
Register
(Index 26h) controls the power management func-
tions. The PR[6:0] bits in this register control the
internal powerdown states of the CS4299. Power-
down control is available for individual subsections
of the CS4299 by asserting any PRx bit or any com-
bination of PRx bits. Most powerdown states can
be resumed by clearing the corresponding PRx bit.
Table 11 shows the mapping of the power control
bits to the functions they manage.
When PR0 is ‘set’, the L/R ADCs and the Input
Mux are shut down and the ADC bit in the Power-
down Control/Status Register (Index 26h) is
‘cleared’ indicating the ADCs are no longer in a
ready state. The same is true for the DACs, the an-
alog mixers, and the reference voltage (Vrefout).
When the PR2 or PR3 bit of the mixer is ‘cleared’,
the mixer section will begin a power-on process,
and the corresponding powerdown status bit will be
‘set’ when the hardware is ready.
Shutting down the AC-link by ‘setting’ PR4 causes
the primary Codec to turn off the BIT_CLK and
drive SDATA_IN low. It also ignores SYNC and
SDATA_OUT in their normal capacities. Either a
Cold Reset or a Warm Reset is required to restore
operation to the CS4299. A Cold Reset will restore
all mixer registers to their power-on default values.
A Warm Reset will not alter the values of any mix-
er register, except clearing the PR4 bit in Power-
down Control/Status Register (Index 26h).
The PR5 bit powers down all analog and digital
subsections of the device. A Cold Reset is the only
way to restore operation to the CS4299 after a PR5
global powerdown.
The CS4299 does not automatically mute any input
or output when the powerdown bits are ‘set’. The
software driver controlling the AC ’97 device must
manage muting the input and output analog signals
before putting the part into any power management
state. The definition of each PRx bit may affect a
single subsection or a combination of subsections
within the CS4299. Table 12 on page 35 contains
the matrix of subsections affected by the respective
PRx function. Table 13 on page 35 shows the dif-
ferent operating power consumptions levels for dif-
ferent powerdown functions.
PR Bit
Function
PR0
L/R ADCs and Input Mux Powerdown
PR1
Front DACs Powerdown
PR2
Analog Mixer Powerdown (Vref on)
PR3
Analog Mixer Powerdown (Vref off)
PR4
AC-link Powerdown (BIT_CLK off)*
PR5
Internal Clock Disable
PR6
Alternate Line Out Powerdown
* Applies only to primary codec
Table 11. Powerdown PR Bit Functions
34
DS319PP6
CS4299
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