compliant to the Intel
參數(shù)資料
型號(hào)： CS4299-JQZR
廠商： Cirrus Logic Inc
文件頁數(shù)： 2/52頁
文件大小： 0K
描述： IC CODEC AC 97 W/SRC 48-LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： SoundFusion™
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 18 b，20 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 87
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
CS4299
10
2. GENERAL DESCRIPTION
The CS4299 is a mixed-signal serial audio Codec
compliant to the Intel Audio Codec ‘97 Specifica-
tion, revision 2.1 [1]. It is designed to be paired
with a digital controller, typically located on the
PCI bus or integrated within the system core logic
chip set. The controller is responsible for all com-
munications between the CS4299 and the remain-
der of the system. The CS4299 contains two
distinct functional sections: digital and analog. The
digital section includes the AC-link interface,
S/PDIF interface, serial data port, Sample Rate
Converters, and power management support. The
analog section includes the analog input multiplex-
er (mux), stereo output mixer, mono output mixer,
stereo Analog-to-Digital Converters (ADCs), ste-
reo Digital-to-Analog Converters (DACs), and
their associated volume controls.
2.1
AC-Link
All communication with the CS4299 is established
with a 5-wire digital interface to the controller, as
shown in Figure 7. This interface is called the
AC-link. All clocking for the serial communication
is synchronous to the BIT_CLK signal. BIT_CLK
is generated by the primary audio codec and is used
to clock the controller and any secondary audio co-
decs. Both input and output AC-link audio frames
are organized as a sequence of 256 serial bits form-
ing 13 groups referred to as ‘slots’. During each au-
dio frame, data is passed bi-directionally between
the CS4299 and the controller. The input frame is
driven from the CS4299 on the SDATA_IN line.
The output frame is driven from the controller on
the SDATA_OUT line. The controller is also re-
sponsible for issuing reset commands via the RE-
SET# signal. Following a Cold Reset, the CS4299
is responsible for notifying the controller that it is
ready for operation after synchronizing its internal
functions. The CS4299 AC-link signals must use
the same digital supply voltage as the controller
chip, either +5 V or +3.3 V. See Section 3, AC Link
Frame Definition, for detailed AC-link informa-
tion.
2.2
Control registers
The CS4299 contains a set of AC ’97 compliant
control registers and a set of Cirrus Logic defined
control registers. These registers control the basic
functions and features of the CS4299. Read access-
es of the control registers by the AC ’97 controller
are accomplished with the requested register index
in Slot 1 of a SDATA_OUT frame. The following
SDATA_IN frame will contain the read data in its
CODEC
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
Digital AC’97
Controller
Figure 7. AC-link Connections
10
DS319PP6
CS4299
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