參數(shù)資料
型號(hào): CS4361-CZZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 24/24頁(yè)
文件大小: 0K
描述: IC DAC STER 6CH 103DB 20TSSOP
標(biāo)準(zhǔn)包裝: 74
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 單電源
功率耗散(最大): 455mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類(lèi)型: 6 電壓,單極
采樣率(每秒): 192k
產(chǎn)品目錄頁(yè)面: 757 (CN2011-ZH PDF)
配用: 598-1153-ND - BOARD EVAL FOR CS4361
其它名稱(chēng): 598-1057-5
9
CS4361
Confidential Draft
9/30/11
SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
11. Not all sample rates are supported for all clock ratios. See table “Common Clock Frequencies” on
page 12 for supported ratios and frequencies.
12. In Internal SCLK Mode, the duty cycle must be 50%
±1/2 MCLK period.
13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on data format and
MCLK/LRCK ratio. (See Figures 7-10)
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
0.512
-
50
MHz
MCLK Duty Cycle
45
-
55
%
Input Sample Rate
All MCLK/LRCK ratios combined
256x, 384x, 1024x
256x, 384x
512x, 768x
1152x
128x, 192x
64x, 96x
128x, 192x
Fs
2
84
42
30
50
100
168
216
54
134
67
34
108
216
kHz
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
45
50
55
%
SCLK Pulse Width Low
tsclkl
20
-
ns
SCLK Pulse Width High
tsclkh
20
-
ns
SCLK Duty Cycle
45
50
55
%
SCLK rising to LRCK edge delay
tslrd
20
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
ns
SDIN valid to SCLK rising setup time
tsdlrs
20
-
ns
SCLK rising to SDIN hold time
tsdh
20
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
-50
-
%
SCLK Period
tsclkw
--
ns
SCLK rising to LRCK edge
tsclkr
--
s
SDIN valid to SCLK rising setup time
tsdlrs
--
ns
SCLK rising to SDIN hold time
MCLK / LRCK =1152, 1024, 512, 256, 128, or 64
tsdh
--
ns
SCLK rising to SDIN hold time
MCLK / LRCK = 768, 384, 192, or 96
tsdh
--
ns
109
SCLK
----------------
tsclkw
2
------------------
109
512
Fs
----------------------10
+
109
512
Fs
----------------------15
+
109
384
Fs
----------------------15
+
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