參數(shù)資料
型號: CS4361-CZZ
廠商: Cirrus Logic Inc
文件頁數(shù): 7/24頁
文件大?。?/td> 0K
描述: IC DAC STER 6CH 103DB 20TSSOP
標準包裝: 74
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 6
電壓電源: 單電源
功率耗散(最大): 455mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 6 電壓,單極
采樣率(每秒): 192k
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
配用: 598-1153-ND - BOARD EVAL FOR CS4361
其它名稱: 598-1057-5
15
CS4361
Confidential Draft
9/30/11
4.5
Initialization and Power-Down
The initialization and power-down sequence flow chart is shown in Figure 12. The CS4361 enters the pow-
er-down state upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the
internal voltage reference, multi-bit digital-to-analog converters, and switched-capacitor low-pass filters are
powered down. The device will remain in the Power-Down Mode until RST is released and MCLK and LRCK
are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period
to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Final-
ly, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to
the quiescent voltage, VQ.
USER: Apply Power
Wait State
USER: Apply LRCK and MCLK
MCLK/LRCK Ratio Detection
USER: Applied SCLK
USER: Remove
LRCK
USER: change
MCLK/LRCK ratio
SCLK mode = internal
SCLK mode = external
Normal Operation
De-emphasis
available
Analog Output
is Generated
Normal Operation
De-emphasis
not available
Analog Output
is Generated
USER: change
MCLK/LRCK ratio
USER: Apply RST
or remove MCLK
USER: Remove
LRCK
USER: Apply RST
or remove MCLK
USER: Apply MCLK, release RST
Power-Down State
VQ and outputs low
VQ and outputs
ramp down
VQ and outputs
ramp down
VQ and outputs ramp up
USER: No SCLK
Figure 12. CS4361 Initialization and Power-Down Sequence
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