參數(shù)資料
型號(hào): CS4382A-DQZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 17/50頁(yè)
文件大?。?/td> 0K
描述: IC DAC 8CH 114DB 192KHZ 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 680mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 16 電壓,單極
采樣率(每秒): 192k
配用: 598-1524-ND - BOARD EVAL FOR CS4382A DAC
24
DS618F2
CS4382A
4.4
Oversampling Modes
The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3, and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-
speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-speed
Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed Mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
4.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorpo-
rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Filter
Plots” on page 42 for more details).
When in Hardware Mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43.
4.6
De-emphasis
The CS4382A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accom-
modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.
Figure 13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale pro-
portionally with changes in sample rate (Fs) if the input sample rate does not match the coefficient which
has been selected.
LRCK
SCLK
Left Channel
Right Channel
SDINx
654
3210
987
15 14 13 12 11 10
10
654321
0
987
15 14 13 12 11 10
17 16
32 clocks
19 18
Figure 11. Format 4 - Right-Justified 20-bit Data
LRCK
SCLK
Left Channel
Right Channel
SDINx
654
3
210
987
15 14 13 12 11 10
10
654
321
0
987
15 14 13 12 11 10
17 16
32 clocks
Figure 12. Format 5 - Right-Justified 18-bit Data
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