參數(shù)資料
型號: CS4382A-DQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 28/50頁
文件大?。?/td> 0K
描述: IC DAC 8CH 114DB 192KHZ 48-LQFP
標準包裝: 2,000
位數(shù): 24
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 模擬和數(shù)字
功率耗散(最大): 680mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 16 電壓,單極
采樣率(每秒): 192k
配用: 598-1524-ND - BOARD EVAL FOR CS4382A DAC
34
DS618F2
CS4382A
6.1.5
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
6.2
Mode Control 2 (Address 02h)
6.2.1
Digital Interface Format (DIF)
Default = 000 - Format 0 (Left-Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD Mode is selected.
PCM Mode:
The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 7-12.
Note:
While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
to ensure proper switching from one mode to another.
76
543
21
0
Reserved
DIF2
DIF1
DIF0
Reserved
00
000
00
0
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
Left-Justified, up to 24-bit data
0
0
1
IS, up to 24-bit data
1
0
1
0
Right-Justified, 16-bit data
2
0
1
Right-Justified, 24-bit data
3
1
0
Right-Justified, 20-bit data
4
1
0
1
Right-Justified, 18-bit data
5
1
0
Reserved
-
1
Reserved
-
Table 5. Digital Interface Formats - PCM Mode
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