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參數(shù)資料
| 型號： | CS51311GD14 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Synchronous CPU Buck Controller for 12V and 5V Applications |
| 中文描述： | 同步降壓控制器的CPU為12V和5V的應(yīng)用 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 239K |
| 代理商： | CS51311GD14 |
C
10
Application Information: continued
latch to be set. This causes the regulator to stop switching.
During this overcurrent condition, the CS51311 stays off
for the time it takes the COMP pin capacitor to discharge
to its lower 0.25V threshold. As soon as the COMP pin
reaches 0.25V, the Fault latch is reset (no overcurrent con-
dition present) and the COMP pin is charged with a 30μA
current source to a voltage 1.1V greater than the V
FB
volt-
age. Only at this point the regulator attempts to restart nor-
mally by delivering short gate pulses to both FETS. The
CS51311 will operate initially with a duty cycle whose val-
ue depends on how low the V
FB
voltage was during the
overcurrent condition (whether hiccup mode was due to
excessive current or hard short). This protection scheme
minimizes thermal stress to the regulator components,
input power supply, and PC board traces, as the overcur-
rent condition persists. Upon removal of the overload, the
fault latch is cleared, allowing normal operation to resume.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V
2
TM
control topology and requires
no additional external components. The control loop
responds to an overvoltage condition within 200ns, caus-
ing the top MOSFET to shut off, disconnecting the regula-
tor from its input voltage. This results in a “crowbar”
action to clamp the output voltage and prevents damage to
the load. The regulator will remain in this state until the
overvoltage condition ceases or the input voltage is pulled
low. The bottom FET and board trace must be properly
designed to implement the OVP function.
Power-Good Circuit
The Power-Good pin (pin 12) is an open-collector signal
consistent with TTL DC specifications. It is externally
pulled up, and is pulled low (below 0.3V) when the regula-
tor output voltage typically exceeds ± 8.5% of the nominal
output voltage. Maximum output voltage deviation before
Power-Good is pulled low is ± 12%.
Output Enable
On/off control of the regulator outputs can be implement-
ed by pulling the COMP pins low. It is required to pull the
COMP pins below the 1.1V PWM comparator offset volt-
age in order to disable switching on the GATE drivers.
Step 1: Definition of the design specifications
In computer motherboard applications the input voltage
comes from the “silver box” power supply. 5V ± 5% is
used for conversion to output voltage, and 12V ± 5% is
used for the external NFET gate voltage and circuit bias.
The CPU V
CC(CORE)
tolerance can be affected by any or all
of the following reasons:
1) buck regulator output voltage setpoint accuracy;
2) output voltage change due to discharging or charging of
the bulk decoupling capacitors during a load current tran-
sient;
3) output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors, circuit
traces, and vias;
4) output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide a
V
CC(CORE)
that will meet the specified tolerance at the
CPU’s inputs.
The designer must also ensure that the regulator compo-
nent junction temperatures are kept within the manufac-
turer’s specified ratings at full load and maximum ambient
temperature. As computer motherboards become increas-
ingly complex, regulator size also becomes important, as
there is less space available for the CPU power supply.
Step 2: Selection of the Output Capacitors
These components must be selected and placed carefully to
yield optimal results. Capacitors should be chosen to pro-
vide acceptable ripple on the regulator output voltage. Key
specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transi-
tions has to be specified. The output capacitors must hold
the output voltage within these limits since the inductor
current can not change with the required slew rate. The
output capacitors must therefore have a very low ESL and
ESR.
The voltage change during the load current transient is:
V
OUT
=
I
OUT
×
(
+ ESR +
)
,
where
I
OUT
/
t = load current slew rate;
I
OUT
= load transient;
t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
t
TR
= output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula
ESR
MAX
=
,
where
V
ESR
= change in output voltage due to ESR
(assigned by the designer).
Once the maximum allowable ESR is determined, the num-
ber of output capacitors can be found by using the formula
V
ESR
I
OUT
t
TR
C
OUT
ESL
t
CS51311-based V
CC(CORE)
Buck Regulator Design Procedure
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