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參數資料
| 型號： | CS51311GD14 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Synchronous CPU Buck Controller for 12V and 5V Applications |
| 中文描述： | 同步降壓控制器的CPU為12V和5V的應用 |
| 文件頁數： | 11/19頁 |
| 文件大小： | 239K |
| 代理商： | CS51311GD14 |
Application Information: continued
C
11
Number of capacitors =
,
where
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer’s data sheet);
ESR
MAX
= maximum allowable ESR.
The actual output voltage deviation due to ESR can then be
verified and compared to the value assigned by the design-
er:
V
ESR
=
I
OUT
×
ESR
MAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESL
MAX
=
,
where
I/
T = load current slew rate (as high as 20A/μs);
V
ESL
= change in output voltage due to ESL.
The actual maximum allowable ESL can be determined by
using the equation:
ESL
MAX
=
,
where ESL
CAP
= maximum ESL per capacitor (it is estimat-
ed that a 10
×
12mm Aluminum Electrolytic capacitor has
approximately 4nH of package inductance).
The actual output voltage deviation due to the actual maxi-
mum ESL can then be verified:
V
ESL
=
.
The designer now must determine the change in output
voltage due to output capacitor discharge during the tran-
sient:
V
CAP
=
,
where
t
TR
= the output voltage transient response time
(assigned by the designer);
V
CAP
= output voltage deviation due to output capaci-
tor discharge;
I = Load step.
The total change in output voltage as a result of a load cur-
rent transient can be verified by the following formula:
V
OUT
=
V
ESR
+
V
ESL
+
V
CAP
Step 3: Selection of the Duty Cycle,
Switching Frequency, Switch On-Time (T
ON
)
and Switch Off-Time (T
OFF
)
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
Duty Cycle = D =
,
where
V
OUT
= buck regulator output voltage;
V
HFET
= high side FET voltage drop due to R
DS(ON)
;
V
L
= output inductor voltage drop due to inductor wire
DC resistance;
V
DROOP
= droop (current sense) resistor voltage drop;
V
IN
= buck regulator input voltage;
V
LFET
= low side FET voltage drop due to R
DS(ON)
.
Step3a: Calculation of Switch On-Time
The switch On-Time (time during which the switching
MOSFET in a synchronous buck topology is conducting) is
determined by:
T
ON
=
,
where F
SW
= regulator switching frequency selected by the
designer.
Higher operating frequencies allow the use of smaller
inductor and capacitor values. Nevertheless, it is common
to select lower frequency operation because a higher fre-
quency results in lower efficiency due to MOSFET gate
charge losses. Additionally, the use of smaller inductors at
higher frequencies results in higher ripple current, higher
output voltage ripple, and lower efficiency at light load
currents.
Step 3b: Calculation of Switch Off-Time
The switch Off-Time (time during which the switching
MOSFET is not conducting) can be determined by:
T
OFF
=
T
ON
,
The C
OFF
capacitor value has to be selected in order to set
the Off-Time, T
OFF
, above:
C
OFF
=
,
where
3980 is a characteristic factor of the CS51311;
D = Duty Cycle.
Step 4: Selection of the Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the induc-
tor value will decrease output voltage ripple, but degrade
transient response. There are many factors to consider in
selecting the inductor including cost, efficiency, EMI and
ease of manufacture. The inductor must be able to handle
the peak current at the switching frequency without satu-
rating, and the copper resistance in the winding should be
kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic
cores that could be used for this application. Among them
are ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. Powdered iron cores are very com-
monly used. Powdered iron cores are very suitable due to
Period
×
(1
D)
3980
1
F
SW
Duty Cycle
F
SW
V
OUT
+ (V
HFET
+ V
L
+ V
DROOP
)
V
IN
+ V
LFET
V
HFET
V
L
I
×
t
TR
C
OUT
ESL
MAX
×
I
t
ESL
CAP
Number of output capacitors
V
ESL
×
t
I
ESR
CAP
ESR
MAX
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