參數(shù)資料
型號: CS51311GD14
廠商: ZF Electronics Corporation
英文描述: Synchronous CPU Buck Controller for 12V and 5V Applications
中文描述: 同步降壓控制器的CPU為12V和5V的應(yīng)用
文件頁數(shù): 18/19頁
文件大?。?/td> 239K
代理商: CS51311GD14
Application Information: continued
C
18
The input filter inductor may not be required because bulk
filter and bypass capacitors, as well as other loads located
on the board will tend to reduce regulator di/dt effects on
the circuit board and input power supply. Placement of the
power component to minimize routing distance will also
help to reduce emissions.
When laying out the CPU buck regulator on a printed cir-
cuit board, the following checklist should be used to
ensure proper operation of the CS51311.
1) Rapid changes in voltage across parasitic capacitors and
abrupt changes in current in parasitic inductors are major
concerns for a good layout.
2) Keep high currents out of sensitive ground connections.
3) Avoid ground loops as they pick up noise. Use star or
single point grounding.
4) For high power buck regulators on double-sided PCBs a
single ground plane (usually the bottom) is recommended.
5) Even though double sided PCBs are usually sufficient
for a good layout, four-layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the two
internal layers as the Power and Gnd planes, the top layer
for the power connections, and component vias, and the
bottom layer for noise sensitive traces.
6) Keep the inductor switching node small by placing the
output inductor, switching and synchronous FETs close
together.
7) The MOSFET gate traces to the IC must be as short,
straight, and wide as possible.
8) Use fewer, but larger output capacitors, keep the capaci-
tors clustered, and use multiple layer traces with heavy
copper to keep the parasitic resistance low.
9) Place the switching MOSFET as close to the +5V input
capacitors as possible.
10) Place the output capacitors as close to the load as
possible.
11) Place the V
FB
,V
OUT
filter resistors (510
) in series with
the V
FB
and V
OUT
pins as close as possible to the pins.
12) Place the C
OFF
and COMP capacitor as close as possible
to the C
OFF
and COMP pins.
13) Place the current limit filter capacitor between the V
FB
and V
OUT
pins, as close as possible to the pins.
14) Connect the filter components of the following pins:
V
FB
, V
OUT
, C
OFF
, and COMP to the Gnd pin with a single
trace, and connect this local Gnd trace to the output capaci-
tor Gnd.
15) The “Droop” Resistor (embedded PCB trace) has to be
wide enough to carry the full load current.
16) Place the V
CC
bypass capacitor as close as possible to
the IC.
Layout Guidelines
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