- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374166 > CS51311GD14 (ZF Electronics Corporation) Synchronous CPU Buck Controller for 12V and 5V Applications PDF資料下載
參數(shù)資料
| 型號(hào)： | CS51311GD14 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Synchronous CPU Buck Controller for 12V and 5V Applications |
| 中文描述： | 同步降壓控制器的CPU為12V和5V的應(yīng)用 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大小： | 239K |
| 代理商： | CS51311GD14 |
Application Information: continued
C
15
Characteristics section);
F
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
P
LFET(TOTAL)
= P
RMSL
+ P
SWL
,
where
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMSL
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET is
known the maximum FET switch junction temperature can
be calculated:
T
J
= T
A
+ [P
LFET(TOTAL)
×
R
θ
JA
],
where
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
θ
JA
= lower FET junction-to-ambient thermal resistance.
Step 8: Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the CS51311 operating frequency. The aver-
age MOSFET gate charge current typically dominates the
control IC power dissipation.
The IC power dissipation is determined by the formula:
P
CONTROLIC
= I
CC
V
CC
+ P
GATE(H)
+ P
GATE(L)
,
where
P
CONTROLIC
= control IC power dissipation;
I
CC
= IC quiescent supply current;
V
CC
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses are:
P
GATE(H)
= Q
GATE(H)
×
F
SW
×
V
GATE(H)
,
where
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge;
F
SW
= switching frequency;
V
GATE(H)
= upper MOSFET gate voltage.
The lower (synchronous) MOSFET gate driver (IC) losses
are:
P
GATE(L)
= Q
GATE(L)
×
F
SW
×
V
GATE(L)
,
where
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge;
F
SW
= switching frequency;
V
GATE(L)
= lower MOSFET gate voltage.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is
removed through the traces connected to the pins of the IC.
Step 9: Slope Compensation
Voltage regulators for today’s advanced processors are
expected to meet very stringent load transient require-
ments. One of the key factors in achieving tight dynamic
voltage regulation is low ESR at the CPU input supply
pins. Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that there’s
very little voltage ramp at the control IC feedback pin (V
FB
)
and regulator sensitivity to noise and loop instability are
two undesirable effects that can surface. The performance
of the CS51311-based CPU V
CC(CORE)
regulator is
improved when a fixed amount of slope compensation is
added to the output of the PWM Error Amplifier (COMP
pin) during the regulator Off-Time. Referring to Figure 11,
the amount of voltage ramp at the COMP pin is dependent
on the gate voltage of the lower (synchronous) FET and the
value of resistor divider formed by R1and R2.
V
SLOPECOMP
= V
GATE(L)
×
(
)
×
(1
e ),
where
V
SLOPECOMP
= amount of slope added;
V
GATE(L)
= lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t
OFF
(switch off-time);
τ
= RC constant determined by C1 and the parallel com-
bination of R1, R2 (Figure 11), neglecting the low driver
output impedance
The artificial voltage ramp created by the slope compensa-
tion scheme results in improved control loop stability pro-
vided that the RC filter time constant is smaller than the
off-time cycle duration (time during which the lower MOS-
FET is conducting).
Step 10: Selection of Current Limit Filter Components
The current limit filter is implemented by a 0.1μF ceramic
capacitor across and two 510
resistors in series with the
V
FB
and V
OUT
current limit comparator input pins. They
provide a time constant
τ
= RC = 100μs, which enables the
circuit to filter out noise and be immune to false triggering,
caused by sudden and fast load changes. These load tran-
sients can have slew rates as high as 20A/μs.
Adaptive voltage positioning is used to help keep the out-
put voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the
full load current and should be chosen so that both DC and
AC tolerance limits are met. An embedded PC trace resis-
tor has the distinct advantage of near zero cost implemen-
tation. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation caused by varia-
tion in the thickness of the PCB layer; 2) the mismatch of
L/W; and 3) temperature variation.
1) Sheet Resistivity
For one ounce copper, the thickness variation is typically
“Droop” Resistor for Adaptive Voltage Positioning
and Current Limit
-t
R2
R1 + R2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS51312GDR16 | Synchronous CPU Buck Controller for 12V Only Applications |
| CS51312 | Synchronous CPU Buck Controller for 12V Only Applications |
| CS51312GD16 | Synchronous CPU Buck Controller for 12V Only Applications |
| CS51313GD16 | Micropower 5V, 100mA Low Dropout Linear Regulator |
| CS51313GDR16 | Micropower 5V, 100mA Low Dropout Linear Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS-51313D16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Mode SMPS Controller |
| CS-51313DR16 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Current-Mode SMPS Controller |
| CS51313GDR16 | 制造商:Rochester Electronics LLC 功能描述: 制造商:ON Semiconductor 功能描述: |
| CS-5132 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual Output CPU Buck Controller |
| CS5132DW24 | 制造商:ON Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。