參數(shù)資料
型號(hào): CS5372-BSZR
廠商: Cirrus Logic Inc
文件頁數(shù): 3/22頁
文件大?。?/td> 0K
描述: IC MODULATOR LP/HP 2CH 24-SSOP
標(biāo)準(zhǔn)包裝: 1,000
類型: 調(diào)制器
分辨率(位): 24 b
采樣率(每秒): 512k
電壓電源: 模擬和數(shù)字,雙 ±
電源電壓: ±2.5V,3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
配用: 598-1778-ND - EVALUATION BOARD FOR CS5376
CS5371 CS5372
DS255F3
11
input signal is a steady state DC signal within
±50 mV of the common mode input voltage. Idle
tones result from patterns in the output bitstream
and appear in the measurement spectrum about
-135 dB down from full scale.
Idle tones can be eliminated by adding differential
DC offset to the modulator inputs. The added off-
set should be applied differentially to the inputs,
common mode offsets do not affect idle tones.
5.1.
Offset Enable - OFST
If the analog inputs are near the common mode
voltage when no signal is present, the OFST pin
can be used to eliminate idle tones.
When
OFST=1, -50 mV of differential offset is added to
the modulator analog inputs to push the idle tones
out of the measurement bandwidth. Care should
be taken that when OFST is active, offset voltages
generated by external circuitry do not negate the
internally added offset.
5.2.
Offset Drift
Offset drift characteristics vary from part to part
and with changes in the power supply voltages. If
the CS5371/72 is used in precision DC measure-
ment applications where offset drift is to be mini-
mized,
the
power
supplies
should
be
well
regulated.
For the lowest offset drift, the CS5371/72 modula-
tors should operate with an MCLK of 2.048 MHz.
The offset drift rate is inversely proportional to
clock frequency, with slower modulator clock rates
exhibiting more offset drift.
Operating from an
MCLK of 1.024 MHz results in twice the offset drift
rate compared to an MCLK of 2.048 MHz.
Because offset drift is not linear with temperature,
an exact drift rate per °C cannot be specified. The
CS5371/72 modulators will exhibit approximately
5 ppm/°C of offset drift operating with an MCLK of
2.048 MHz.
6. VOLTAGE REFERENCE INPUTS
The CS5371/72 modulators are designed to oper-
ate with a 2.5 V voltage reference applied across
the VREF+ and VREF- pins to set the full-scale sig-
nal range of the analog inputs. A 2.5 V voltage ref-
erence results in the highest dynamic range and
best signal-to-noise performance, though smaller
reference voltages may be used.
When the
CS5371/72 modulators are operated with a 2.5 V
reference, the analog inputs measure full-scale
signals of 5 volts peak-to-peak fully differential.
In a single supply power configuration the voltage
reference output should be connected to the
VREF+ pin with the VREF- pin connected to
ground. In a dual supply power configuration the
voltage reference should be powered from the VA+
and VA- supplies, with the modulator VREF+ pin
connected to the voltage reference output and the
VREF- pin connected to VA-. Because most 2.5 V
voltage references require a power supply voltage
greater than 3 V to operate, when powering the
voltage reference from dual supplies the reference
voltage into the VREF+ pin should be defined rela-
tive to the VA- supply.
The selected voltage reference should produce
less than 1
Vrms of noise in the measurement
bandwidth on the VREF+ pin. The digital filter out-
put word rate selection determines the bandwidth
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