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參數(shù)資料
| 型號(hào)： | CS5530-ISZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 5/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 1CH W/LNA 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1158-ND - BOARD EVAL FOR CS5530 |
| 其它名稱： | 598-1283-5 |
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CS5530
DS742F3
13
initialization sequence, the user must also perform
a system reset sequence which is as follows: Write
a logic 1 into the RS bit of the configuration regis-
ter. This will reset the calibration registers and
other logic (but not the serial port). A valid reset
will set the RV bit in the configuration register to a
logic 1. After writing the RS bit to a logic 1, wait
8 master clock cycles, then write the RS bit back to
logic 0. Note that the other bits in the configura-
tion register cannot be written on this write cycle
as they are being held in reset until RS is set back
to logic 0. While this involves writing an entire
word into the configuration register to casue the
RS bit to go to logic 0, the RV bit is a read only bit,
therefore a write to the configuration register will
not overwrite the RV bit. After clearing the RS bit
back to logic 0, read the configuration register to
check the state of the RV bit as this indicates that a
valid reset occurred. Reading the configuration
register clears the RV bit back to logic 0.
Completing the reset cycle initializes the on-chip
registers to the following states:
After the configuration register has been read to
clear the RV bit, the register can then be written to
set the other function bits or other registers can be
written or read.
Once the system initialization or reset is complet-
ed, the on-chip controller is initialized into com-
mand mode where it waits for a valid command
(the first 8-bits written into the serial port are shift-
ed into the command register). Once a valid com-
mand is received and decoded, the byte instructs
the converter to either acquire data from or transfer
data to an internal register, or perform a conversion
or a calibration. The Command Register Descrip-
tions section lists all valid commands.
Offset (1 x 32)
Offset Register (1 x 32)
Conversion Data
Register (1 x 32)
Configuration Register (1 x 32)
Power Save Select
Reset System
Input Short
Voltage Reference Select
Output Latch
CS
SDI
SDO
SCLK
Read
On
ly
Command
Register (1 × 8)
Wr
it
e
O
n
ly
Serial
Interface
Data (1 x 32)
Filter Rate Select
Word Rate
Unipolar/Bipolar
Open Circuit Detect
Gain
(1 x 32)
Gain Register (1 x 32)
Figure 6. CS5530 Register Diagram
Configuration Register:
00000000(H)
Offset Register:
00000000(H)
Gain Register
01000000(H)
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參數(shù)描述 |
|---|---|
| CS5530-ISZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 24-Bit 1-ch Low Noise ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5531 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16 BIT AND 24 BIT ADCS WITH ULTRA LOW NOISE PGIA |
| CS5531_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit and 24-bit ADCs with Ultra-low-noise PGIA |
| CS5531-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5531-ASR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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