- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2067 > CS8420-DSZ (Cirrus Logic Inc)IC CONV S/R DGTL AUDIO 28-SOIC PDF資料下載
參數(shù)資料
| 型號： | CS8420-DSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 64/94頁 |
| 文件大小： | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1729 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
DS245F4
67
CS8420
13.5
Hardware Mode 4 Description
(Transceive Data Flow, No SRC)
Hardware mode 4 data flow is shown in Figure 27. Audio data is input via the AES3 receiver, and routed to
the serial audio output port. Different audio data synchronous to RMCK may be input into the serial audio
input port, and output via the AES3 transmitter.
The channel status data, user data, and validity bit information are handled in two alternative modes: 4A
and 4B, determined by a start-up resistor on the COPY pin. In mode 4A, the received PRO, COPY, ORIG,
EMPH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied
from the received channel status data, and the transmitted U and V bits are 0.
In mode 4B, only the COPY and ORIG pins are output, and reflect the received channel status data. The
transmitted channel status bits, user data, and validity bits are input serially via the PRO/C, EMPH/U, and
AUDIO/V pins. Figure 20 shows the timing requirements.
The APMS pin allows the serial audio input port to be set to master or slave.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample is passed unmodified
to the serial audio output port.
Start-up options are shown in Table 13, and allow choice of the serial audio output port as a master or slave,
whether TCBL is an input or an output, the audio serial ports formats, and the source of the transmitted C,
U, and V data.
The following pages contain the detailed pin descriptions for Hardware mode 4.
AES3
Encoder
&Tx
Serial
Audio
Output
AES3 Rx
&
Decoder
C&Ubit Data Buffer
RXP
RXN
OLRCK
OSCLK
SDOUT
TXP
TXN
RMCK
RERR
COPY ORIG EMPH/U AUDIO/V
TCBL
DFC0
DFC1
VD+
H/S
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
VD+
Serial
Audio
Input
ILRCK
ISCLK
SDIN
PRO/C
APMS
Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS8421-CNZ | IC SAMPLE RATE CONVERTER 20QFN |
| CS8427-DZZ | IC TXRX DGTL AUDIO 96KHZ 28TSSOP |
| CY28329ZXC | IC CLOCK CK408B PLUMAS 56SSOP |
| CY28346OXC | IC CLOCK DIFF OUT CK408 56SSOP |
| CY28346ZI-2 | IC CLOCK DIFF OUT CK408 56TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS8420-DSZR | 功能描述:音頻 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| CS8421 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
| CS8421_06 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_09 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192 kHz Asynchronous Sample Rate Converter |
| CS8421_10 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit, 192-kHz Asynchronous Sample Rate Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。