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參數(shù)資料
| 型號： | CS8420-DSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 81/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV S/R DGTL AUDIO 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 類型： | 采樣率轉(zhuǎn)換器 |
| 應(yīng)用： | 數(shù)字音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 其它名稱： | 598-1729 |
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82
DS245F4
CS8420
15.1.1
Manually Accessing the E Buffer
The user can monitor the data being transferred by reading the E buffer, which is mapped into the register
space of the CS8420, via the control port. The user can modify the data to be transmitted by writing to the
E buffer.
The user can configure the interrupt enable register to cause interrupts to occur whenever D-to-E or E-to-
F buffer transfers occur. This allows determination of the allowable time periods to interact with the E buff-
er.
Also provided are D-to-E and E-to-F inhibit bits. The associated buffer transfer is disabled whenever the
user sets these bits. These may be used whenever “l(fā)ong” control port interactions are occurring. They can
also be used to align the behavior of the buffers with the selected audio data flow. For example, if the
audio data flow is serial port in to AES3 out, then it is necessary to inhibit D-to-E transfers, since these
would overwrite the desired transmit C data with invalid data.
Flowcharts for reading and writing to the E buffer are shown in Figures 39 and 40. For reading, since a D-
to-E interrupt just occurred, then there a substantial time interval until the next D-to-E transfer (approxi-
mately 192 frames worth of time). This is usually plenty of time to access the E data without having to
inhibit the next transfer. For writing, the sequence starts after a E-to-F transfer, which is based on the out-
put timebase. Since a D-to-E transfer could occur at any time (this is based on the input timebase), then
it is important to inhibit D-to-E transfers while writing to the E buffer until all writes are complete. Then wait
until the next E-to-F transfer occurs before enabling D-to-E transfers. This ensures that the data written
to the E buffer actually gets transmitted and not overwritten by a D-to-E transfer.
If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calcu-
lated by the CS8420, and does not have to be written into the last byte of the block by the host microcon-
troller.
block 1
block 2
block 3
block 4
block 5
block 1
block 2
block 3
block 4
block 5
Contents of E buffer
Updated at Fsi rate
Contents of F buffer
Updated from E
Output at Fso rate
Fso > Fsi (3/2) Causes blocks 1 and 3 to be transmitted twice
Fso < Fsi (2/3) Causes blocks 3 and 6 to not be transmitted
Contents of E buffer
Updated at Fsi rate
Contents of F buffer
Updated from E
Output at Fso rate
block 1
block 2
block 3
block 4
block 5
block 6
block 7
block 1
block 2
block 4
block 5
block 7
Figure 38. Channel Status Block Handling When Fso is Not Equal to Fsi
D to E interrupt occurs
Optionally set D to E inhibit
Read E data
If set, clear D to E inhibit
Return
Figure 39. Flowchart for Reading the E Buffer
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相關(guān)代理商/技術(shù)參數(shù) |
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| CS8420-DSZR | 功能描述:音頻 DSP IC Digital Audio Sample Rate Convertr RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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