參數(shù)資料
型號: CXD2529Q
廠商: Sony Corporation
元件分類: 數(shù)字信號處理
英文描述: CD Digital Signal Processor
中文描述: CD數(shù)字信號處理器
文件頁數(shù): 4/64頁
文件大?。?/td> 675K
代理商: CXD2529Q
– 4 –
CXD2529Q
Pin Description
Pin
No.
Symbol
I/O
Description
Power supply (+5V).
GND.
Left-channel zero detection flag.
Right-channel zero detection flag.
TEST output pin; normally open.
Master clock frequency-divider output. Selects and outputs XTAI
×
1,
×
1/2,
×
1/4 or low only.
SQSO readout clock input.
Sub Q 80-bit serial output.
SENS output to CPU.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
SENS input from SSP.
Track jump count signal input.
Serial data output to SSP.
Serial data latch output to SSP. Latched at the falling edge.
Serial data transfer clock output to SSP.
Microcomputer extended interface (input A).
Microcomputer extended interface (input B).
Microcomputer extended interface (input C).
Microcomputer extended interface (input D).
Microcomputer extended interface (output).
Focus OK input.
Used for SENS output and the servo auto sequencer.
Power supply (+5V).
GND.
Spindle motor on/off control output.
Spindle motor servo control.
Spindle motor servo control.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
Spindle motor external control input.
TEST pin; normally GND.
TEST pin; normally GND.
Wide-band EFM PLL charge pump output. Turned on/off by FCSW of
address E.
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, Z, 0
1, 0
1, Z, 0
O
O
O
O
I
O
O
I
I
I
I
I
O
O
O
I
I
I
I
O
I
O
O
O
O
I
I
I
O
V
DD
V
SS
LMUT
RMUT
TES2
CKOUT
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
SPOC
SPOD
XLON
FOK
V
DD
V
SS
MON
MDP
MDS
LOCK
PWMI
TES0
TES1
VPCO2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
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