參數(shù)資料
型號(hào): CXD2548
廠商: Sony Corporation
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: CD Digital Signal Processor with Built-in Digital Servo and DAC
中文描述: CD數(shù)字信號(hào)處理器,具有內(nèi)置數(shù)字伺服和DAC
文件頁(yè)數(shù): 87/113頁(yè)
文件大小: 1286K
代理商: CXD2548
– 87 –
CXD2548R
§4-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. However, the used TZC signal can be selected and
there are two types of output methods according to the COUT signal application.
For 1-track jumps, etc.
Fast phase COUT signal generation with a fast phase TZC signal.
For High-speed traverse
Reliable COUT signal generation with a delayed phase TZC signal.
This is because some time is required to generate the MIRR signal, and it is necessary to delay the TZC signal
in accordance with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D16 when D19 = D18 = 1 and D17 = 0 are set with $3.
(When D16 = 1, for delayed phase and high-speed traverse.) In addition, the TZC signal delay can be selected
from two values with D14 of $36.
§4-14. Serial Readout Circuit
The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by $39. (See Fig. 4-12, Table 4-6 and "Description of SENS Signals".)
Specified commands
$390C
$3908
$3904
$391F
$3953
$3963
$391C
$391D
VC AVRG measurement result
FE AVRG measurement result
TE AVRG measurement result
RF AVRG measurement result
FCS AGCNTL coefficient result
TRK AGCNTL coefficient result
TRVSC adjustment result
FBIAS register value
···
···
t
DLS
t
SPW
1/f
SCLK
MSB
LSB
XLAT
SCLK
Serial Read Out Data
(SENS)
Item
Symbol
Min.
Typ.
Max.
Unit
SCLK frequency
SCLK pulse width
Delay time
f
SCLK
t
SPW
t
DLS
500
15
1
MHz
ns
μs
Table 4-6.
During readout, the upper 8 bits of the serial data must be 39 (Hex).
Fig. 4-12.
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