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參數(shù)資料
| 型號(hào)： | CXD2548 |
| 廠商： | Sony Corporation |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| 中文描述： | CD數(shù)字信號(hào)處理器，具有內(nèi)置數(shù)字伺服和DAC |
| 文件頁數(shù)： | 96/113頁 |
| 文件大?。?/td> | 1286K |
| 代理商： | CXD2548 |
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– 96 –
CXD2548R
$3A
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
FBON FBSS FBUP FBV1 FBV0
0
TJD0 FPS1 FPS0 TPS1 TPS0 CEIT SJHD INBK MTI0
FBON:
FBIAS (focus bias) register addition (on/off)
The FBIAS register value is added to the signal loaded into the FCS In register by setting D14 to
1 (on).
FBIAS (focus bias) register/counter switching
The FCS BIAS register can be used as a counter by setting D13 to 1 (on).
FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1. The FBIAS register functions as a down
counter with D12 set to 0, and as an up counter when set to 1.
FBV1, FBV0: FBIAS (focus bias) counter voltage switching
FCS BIAS count-up steps is decided by these bits.
FBSS:
FBUP:
TJD0:
This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on only
when SFJP = 1 (during surf jump operation).
FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.
TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.
This is effective for increasing the overall gain in order to widen the servo band.
Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,
6dB, 12dB and 18dB can be selected independently for focus (tracking) by setting the relative
gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.
CEIT:
The CE pin input takes over the TE pin input by setting D3 to 1 (on). This means that the
registers and filters for TE input are used for CE input.
This holds the tracking filter output at the value when surf jump starts during surf jump.
When D2 is 0 (off), the brake circuit masks the tracking filter output signal with TRKCNCL which
is generated by taking the MIRR signal at the TZC edge. When D2 is set to 1 (on), the tracking
filter input is masked instead of the output.
The tracking filter input is masked when the MIRR signal is high by setting D1 to 1 (on).
SJHD:
INBK:
MT10:
The counter changes once for each
sampling cycle of the focus servo filter.
When MCK is 128Fs, the sampling
frequency is 88.2kHz. When converted to
FE input, 1 step is approximately 3.9 [mV].
FBV1
0
0
1
1
0
1
0
1
1
2
4
8
FBV0
Number of steps
FPS1
0
0
1
1
FPS0
0
1
0
1
0dB
+6dB
+12dB
+18dB
Relative gain
TPS1
0
0
1
1
TPS0
0
1
0
1
0dB
+6dB
+12dB
+18dB
Relative gain
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| CXD2552Q | 1 BIT D/A CONVERTER |
| CXD2597Q | CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2720Q-2 | CAP 10UF 50V 20% TANT SMD-7343-43 TR-13 GOLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD2548R | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD Digital Signal Processor with Built-in Digital Servo and DAC |
| CXD2550P | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Digital Filter for CD |
| CXD2551M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| CXD2551M/P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| CXD2551P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
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