參數(shù)資料
型號(hào): CXD3511Q
廠商: Sony Corporation
英文描述: Digital Signal Driver/Timing Generator
中文描述: 數(shù)字信號(hào)驅(qū)動(dòng)器/時(shí)序發(fā)生器
文件頁(yè)數(shù): 58/79頁(yè)
文件大小: 531K
代理商: CXD3511Q
58
CXD3511Q
(l) VST and VCK pulse settings
(1) VST1P[11:2] and VST2P[11:2] (sub addresses: 026h to 027h)
These set the VSTL and VSTR pulse rise and fall positions within 1H in 10 bits. The position can be set in 4-dot
units using the internal HP counter "0" position as the reference. Set the "(Tvstp
4)/4" value.
See the FRVC1LNK, RGVLNK and RGT settings hereafter to determine which of the VST1P or VST2P
settings is reflected to VSTL or VSTR.
Tvckp
HDIN
HP counter
VST
VCK
Tvstp
0
(2) VCK1P[10:1] and VCK2P[10:1] (sub addresses: 024h to 025h)
These set the VCKL, VCKR, FRP and XFRP inversion positions within 1H in 10 bits. The inversion positions
can be set in 2-dot units using the internal HP counter "0" position as the reference. Set the "(Tvckp
2)/2"
value.
See the FRVC1LNK, RGVLNK and RGT settings hereafter to determine which of the VCK1P VCK2P or FRPP
settings is reflected to VCKL or VCKR.
(3) VSTFIX and VCKFIX (sub address: 002h), VSTPOL and VCKPOL (sub address: 001h)
These set the VST and VCK pulse output polarities. The VSTL and VSTR pulse polarities and the VCKL and
VCKR pulse polarities relative to the VSTL and VSTR pulses change as follows according to the combination
of linked/not linked with control signal DWN.
(4) V1OE (sub address: 02Dh)
This sets the output limit of VSTL, VCKL and ENBL pulses.
Setting value: 1 = VSTL, VCKL and ENBL pulses are output, 0 = Output is fixed to "0"
(5) V2OE (sub address: 02Dh)
This sets the output limit of VSTR, VCKR and ENBR pulses.
Setting value: 1 = VSTR, VCKR and ENBR pulses are output, 0 = Output is fixed to "0"
FIX
0
0
0
0
1
1
1
1
POL
0
0
1
1
0
0
1
1
DWN
0
1
0
1
0
1
0
1
Output polarity
Positive
Negative
Negative
Positive
Negative
Negative
Positive
Positive
: VST or VCK
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