參數(shù)資料
型號(hào): CXD3511Q
廠商: Sony Corporation
英文描述: Digital Signal Driver/Timing Generator
中文描述: 數(shù)字信號(hào)驅(qū)動(dòng)器/時(shí)序發(fā)生器
文件頁(yè)數(shù): 60/79頁(yè)
文件大小: 531K
代理商: CXD3511Q
60
CXD3511Q
(n) VCK and FRP transition point shared setting and V block pulse right/left inversion link setting
FRVC1LNK and RGVLNK (sub address: 003h)
These set the VCKL and VCKR transition points
Setting value: 1 = FRP and VCK transition points are shared,
0 = FRP and VCK transition points are independent
When FRVC1LNK = 1, the VCK inversion timing is forcibly synchronized with the FRP inversion timing. At this
time, which of VCKL or VCKR is linked with the FRP transition point is as follows.
When FRVC1LNK = 0, the VCKL and VCKR transition points are determined by VCK1P[10:1] or VCK2P[10:1]
according to the RGT setting. When RGVLNK = 1, the V block pulses, VSTL, VCKL and ENBL are switched
with VSTR, VCKR and ENBR, respectively, linked with right/left inversion control signal RGT. When RGVLNK =
0, the V block pulses are fixed regardless of the RGT setting. See the following page for a detailed description.
VCK1P
FRPP
VCK2P
VCKL
VCKR
FRP
A
VCKL
FRPP
FRP
VCK1P
VCK2P
VCKR
B
VCKL
FRPP
FRP
VCK2P
VCKR
D
VCKL
VCKR
VCK2P
C
FRPP
FRP
FRVC1LNK
0
0
0
0
1
1
1
1
RGVLNK
0
0
1
1
0
0
1
1
RGT
0
1
0
1
0
1
0
1
Output waveform
A
A
B
A
C
C
D
C
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