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參數資料
| 型號： | CXD8302Q |
| 廠商： | Sony Corporation |
| 英文描述： | PLL For CCD Cameras(用于CCD照相機的鎖相環(huán)電路) |
| 中文描述： | CCD相機的PLL（用于防治荒漠化公約照相機的鎖相環(huán)電路） |
| 文件頁數： | 4/10頁 |
| 文件大小： | 183K |
| 代理商： | CXD8302Q |
– 4 –
CXD8302Q
Pin No.
Symbol
I/O
Description
38
39
40
41
42
43
44
CLKI
V
DD
V
SS
HD
VD
SYNC
BLK
I
—
—
O
O
O
O
Clock input (from timing generator).
Horizontal sync signal output.
Vertical sync signal output.
Sync signal output.
Blanking pulse output.
Electrical Characteristics
1) DC characteristics
(V
DD
= 5V±0.25V, Topr = 0 to 70°C, V
SS
= 0V)
Item
Symbol
V
IH
V
IL
I
IN
1
I
IN
2
I
IN
3
V
OH
V
OL
Conditions
V
I
= V
DD
V
I
= V
SS
I
OH
= –2mA
I
OL
= 4mA
Min.
0.7V
DD
–10
10
–8
2.4
Typ.
Max.
0.3V
DD
Unit
V
V
μA
μA
μA
V
V
±1
35
–30
4.5
0.2
10
120
–100
0.4
High
Low
High
Low
Input voltage
Input current 1
(Input pins other than those below)
Input current 2
(Input pins with pull-up resistor)
Input current 3
(Input pins with pull-down resistor)
Output voltage
2) AC characteristics
Vertical reset in VD/HD sync mode
The phase of EXTVD should be input as shown in the diagram below against the first equivalent pulse during
vertical blanking period.
(Take care as the following conditions might not be satisfied depending on the phase setting of INTf
H
if the
phases are locked when the falling phase shifts a lot between EXTf
H
and INTf
H
.)
81 clocks
81 clocks
SYNC
EXTVD
The EXTVD should fall at the timing shown with the slashes.
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