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參數資料
| 型號： | CXD8302Q |
| 廠商： | Sony Corporation |
| 英文描述： | PLL For CCD Cameras(用于CCD照相機的鎖相環(huán)電路) |
| 中文描述： | CCD相機的PLL（用于防治荒漠化公約照相機的鎖相環(huán)電路） |
| 文件頁數： | 6/10頁 |
| 文件大?。?/td> | 183K |
| 代理商： | CXD8302Q |
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CXD8302Q
Example of System Configuration
13
14
15
26
19
20
33
38
41
42
7
6
5
Separation
of f
H
and fv
Phase
Comparator
LPF
VCO
Frequency Division/
Pulse Generation Circuit
1/2
Frequency
Division
Pulse
Generation
Circuit
CLK
HD
VD
CXD8302Q
CXD2422R (TG)
INTf
H
EXTf
H
f
H
f
V
SYNC
HD
VD
MODE1
External sync signal
Electronic shutter serial data
XH1, 2
XRG
XSUB
XV1 to 4
XSG1, 2
SHP, SHD
HCLP1, 2
VCLP
PBLK
To each
driver
To signal
processing
circuit
36MHz (Component digital)
35.79545MHz (Composite digital, EIA)
35.56895MHz (Composite digital, CCIR)
Note)
1. Either SYNC or VD/HD is used as the external sync signal.When SYNC is used (SYNC synchronous
mode), fix MODE1 to High; when VD/HD is used (VD/HD synchronous mode), fix MODE1 to Low.
2. Be sure to do phase comparison of the falling edge of EXTf
H
and INTf
H
for SYNC synchronous
mode.
3) INTf
H
phase setting
In either VD/HD or SYNC sync mode, the INTf
H
phase should be adjusted in line with the phase variance of
EXTf
H
, which forms the reference for phase comparison. The INTf
H
phase may be adjusted against VD, HD,
SYNC and BLK pulses using DLY0 to DLY7, respectively. (The state of INTf
H
and EXTf
H
phases fixed by PLL
leads to phase adjustment of VD, HD, SYNC, and BLK pulse against the external sync signal.)
The INTf
H
is set to the phase being delayed (DELAY-64) clocks from that of HD.
DELAY = 0 to 255: to be set in 8-bit binary with DLY7 as MSB. High: 1, low: 0.
INTf
H
HD
128 clocks
128 clocks
(DELAY – 64) clocks
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