- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8999 > CY28508OXCT (Silicon Laboratories Inc)IC CLOCK SSCG 3DIFF PAIR 28SSOP PDF資料下載
參數(shù)資料
| 型號： | CY28508OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SSCG 3DIFF PAIR 28SSOP |
| 標準包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 333.3MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
CY28508
........................ Document #: 38-07534 Rev. *F Page 4 of 13
Serial Control Registers
Glitch-free operation for both enabling and disabling Spread
Spectrum. To achieve down spread operation, reprogram the
N register to drop the frequency by half the spread amount.
Byte 0 : CPU Control Register
Bit
@Pup
Name
Description
7
HW
LOCK
Lock Detect: 0 = not at final frequency, 1 = VCO locked (read-only).
6
0
SS_ENABLE
0 = disabled, 1 = enabled.
5
0
SST1
Select spread percentage 1. See Table 4
4
1
SST0
Select spread percentage 0. See Table 4
3
1
REF
REF Output Enable
0 = Disabled (three-stated)), 1 = Enabled
2
1
CPUT/C2
CPU2 Output Enable
0 = Disabled (three-stated), 1 = Enabled
1
CPUT/C1
CPU1 Output Enable
0 = Disabled (three-stated), 1 = Enabled
0
1
CPUT/C0
CPU0 Output Enable
0 = Disabled (three-stated), 1 = Enabled
Table 4. Spread Spectrum Table
SST1 SST0
% Spread
00
0.125% Center spread Lexmark profile
01
0.25% Center spread Lexmark profile
10
0.5% Center spread Lexmark profile
11
0.5% Center spread Linear profile
Byte 1: Dial-a-Frequency Control Register N0 [default = 112.35 MHz, N = 43d, ODSEL = 1]
Bit
@Pup
Description
7
0
Test Mode: 0 = normal operation, 1 = phase-locked loop (PLL) bypass mode, when OD = 3 then /3, when
OD = 2 then /2.
6
0
N6, most significant bit (MSB).
51
N5
40
N4
31
N3
20
N2
11
N1
0
1
N0, least significant bit (LSB).
Byte 2: Dial-a-Frequency Control Register M0 [default = 112.35MHz, M = 49d, ODSEL = 1]
Bit
@Pup
Description
7
0
The charge pump current value during Smooth-Track can be programmed to normal mode (2xICP) by
setting this bit to “1.” The default value of “0” (1xICP) will program the charge pump current to half of normal
and will reduce the bandwidth and hence the slew rate.
6
Pin 6
FSEL operational status, whether HW or SW. 0 = M&N0, 1 = M&N1 (read only).
5
1
M5 MSB
41
M4
30
M3
20
M2
10
M1
01
M0, LSB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-JTF-MZ-F2 | CONVERTER MOD DC/DC 72V 25W |
| LTC2601CDD-1#PBF | IC DAC 16BIT R-R 10-DFN |
| VI-JT4-MZ-F4 | CONVERTER MOD DC/DC 48V 25W |
| AD5313ARUZ | IC DAC 10BIT DUAL R-R 16-TSSOP |
| VI-JT4-MZ-F3 | CONVERTER MOD DC/DC 48V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28510 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28510OC | 制造商:Rochester Electronics LLC 功能描述:PERIPHERAL I/O CLOCK GENERATOR - Bulk |
| CY28510OCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Peripheral I/O Clock Generator |
| CY28512ZC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28512ZC-2T | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。