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參數(shù)資料
| 型號： | CY28551LFXC-3 |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK INTEL/AMD SIS VIA 56QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，AMD CPU |
| 輸入： | 晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 56-QFN（8x8） |
| 包裝： | 托盤 |
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CY28551-3
......................Document #: 001-05677 Rev. *D Page 5 of 28
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2. The block write and block read
sponding byte write and byte read protocol. The slave receiver
address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address – 7 bits
8:2
Slave address – 7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code – 8 bits
18:11
Command Code – 8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
Repeat start
28
Acknowledge from slave
27:21
Slave address – 7 bits
36:29
Data byte 1 – 8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
45:38
Data byte 2 – 8 bits
37:30
Byte Count from slave – 8 bits
46
Acknowledge from slave
38
Acknowledge
....
Data Byte/Slave Acknowledges
46:39
Data byte 1 from slave – 8 bits
....
Data Byte N – 8 bits
47
Acknowledge
....
Acknowledge from slave
55:48
Data byte 2 from slave – 8 bits
....
Stop
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave – 8 bits
....
NOT Acknowledge
....
Stop
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
1Start
8:2
Slave address – 7 bits
8:2
Slave address – 7 bits
9Write
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28551LFXC-3T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28551LFXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY2862-000 | 制造商:TE Connectivity 功能描述:82A0111-4-9-G110 |
| CY2863-000 | 制造商:TE Connectivity 功能描述:82A0111-8-9-G110 - Bulk |
| CY28800 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:100-MHz Differential Buffer for PCI Express and SATA |
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