參數(shù)資料
型號(hào)： CY28551LFXC-3
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK INTEL/AMD SIS VIA 56QFN
標(biāo)準(zhǔn)包裝： 260
類型： 時(shí)鐘/頻率發(fā)生器
PLL： 是
主要目的： Intel CPU，AMD CPU
輸入： 晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:20
差分 - 輸入:輸出： 無/是
頻率 - 最大： 400MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 56-QFN（8x8）
包裝： 托盤
CY28551-3
....................Document #: 001-05677 Rev. *D Page 12 of 28
Crystal Recommendations
The CY28551-3 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28551-3 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Byte 17: Control Register 17
Bit
@Pup
Type
Name
Description
7
0
R/W
Recovery N7
Watchdog Recovery Bit
6
0
R/W
Recovery N6
Watchdog Recovery Bit
5
0
R/W
Recovery N5
Watchdog Recovery Bit
4
0
R/W
Recovery N4
Watchdog Recovery Bit
3
0
R/W
Recovery N3
Watchdog Recovery Bit
2
0
R/W
Recovery N2
Watchdog Recovery Bit
1
0
R/W
Recovery N1
Watchdog Recovery Bit
0
R/W
Recovery N0
Watchdog Recovery Bit
Byte 18: Control Register 18
Bit
@Pup
Type
Name
Description
7
0
R/W
PCIE_N8
PCI-E Dial-A-Frequency Bit N8
6
0
R/W
FS[D:A]
FS_Override
0 = Select operating frequency by FS(D:A) input pins
1 = Select operating frequency by FSEL_(3:0) settings
5
0
R/W
DF_EN
Dynamic Frequency for CPU frequency Enable
0 = Disable, 1 = Enable
4
0
R/W
RESET_I_EN
RESET_I# Enable
0: Disable, 1: Enable.
3
0
R/W
Prog_PCIE_EN
Programmable SRC frequency enable
0 = Disabled, 1 = Enabled.
2
0
R/W
Prog_CPU_EN
Programmable CPU frequency enable
0 = Disabled, 1 = Enabled.
1
0
R/W
Watchdog Autore-
covery
Watchdog Autorecovery Mode
0 = Disable (Manual), 1= Enable (Auto)
0
R/W
Recovery N8
Watchdog Recovery Bit
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
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CY28551LFXC-3T 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Universal System Clk Intel AMD SiS Via RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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