參數(shù)資料
型號(hào): CY28551LFXC-3
廠商: Silicon Laboratories Inc
文件頁數(shù): 28/28頁
文件大小: 0K
描述: IC CLOCK INTEL/AMD SIS VIA 56QFN
標(biāo)準(zhǔn)包裝: 260
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU,AMD CPU
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:20
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-QFN(8x8)
包裝: 托盤
CY28551-3
......................Document #: 001-05677 Rev. *D Page 9 of 28
0
R
Vendor ID Bit 0
Byte 7: Vendor ID (continued)
Bit
@Pup
Type
Name
Description
Byte 8: Control Register 8
Bit
@Pup
Type
Name
Description
7
0
R/W
RESERVED
RESERVED, Set = 0
6
0
R/W
CR1_PCIEX6
PCIEX[T/C]6 CLKREQ#A Control
1 = PCIEX [T/C]6 stoppable by CLKREQ#A pin
0 = Free running
5
0
R/W
CR1_PCIEX5
PCIEX[T/C]5 CLKREQ#B Control
1 = PCIEX [T/C]5 stoppable by CLKREQ#B pin
0 = Free running
4
0
R/W
CR1_PCIEX4
PCIEX[T/C]4 CLKREQ#B Control
1 = PCIEX [T/C]4 stoppable by CLKREQ#B pin
0 = Free running
3
0
R/W
RESERVED
RESERVED, Set = 0
2
0
R/W
RESERVED
RESERVED, Set = 0
1
0
R/W
RESERVED
RESERVED, Set = 0
0
R/W
RESERVED
RESERVED, Set = 0
Byte 9: Control Register 9
Bit
@Pup
Type
Name
Description
7
0
R/W
DF3_N8
The DF3_N[8:0] will be used to configure CPU frequency for Dynamic
Frequency. DOC[1:2] =11
6
0
R/W
DF2_N8
The DF2_N[8:0] will be used to configure CPU frequency for Dynamic
Frequency. DOC[1:2] =10
5
0
R/W
DF1_N8
The DF1_N[8:0] will be used to configure CPU frequency for Dynamic
Frequency. DOC[1:2] =01
4
0
R/W
RESERVED
RESERVED, Set = 0
3
0
R/W
RESERVED
RESERVED, Set = 0
2
0
R/W
SMSW_Bypass
Smooth switch Bypass
0: Activate SMSW block
1: Bypass and de-activate SMSW block.
1
0
R/W
SMSW_SEL
Smooth switch select
0: select CPU_PLL
1: select SRC_PLL.
0
R/W
RESERVED
RESERVED, Set = 0
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