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參數(shù)資料
| 型號： | CY38050V484-125BBI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | LOADABLE PLD, 10 ns, PBGA484 |
| 封裝： | 1 MM PITCH, FBGA-484 |
| 文件頁數(shù)： | 44/45頁 |
| 文件大?。?/td> | 720K |
| 代理商： | CY38050V484-125BBI |
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Quantum38K ISR
CPLD Family
Document #: 38-03043 Rev. *G
Page 8 of 45
I/O Banks
The Quantum38K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are eight I/O
banks per device as shown in Figure 6, and all I/Os from an
I/O bank are located in the same section of a package for PCB
layout convenience.
Quantum38K devices support True Vertical Migration, i.e.,
for each package type, Quantum38K devices of different
densities keep given pins in the same I/O banks. This allows
for easy and simple implementation of multiple I/O standards
during the design and prototyping phase, before a final density
has been determined.
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
Each I/O bank can use any supported I/O standard by
supplying appropriate VCCIO voltages. All the VCCIO pins in an
I/O bank must be connected to the same VCCIO voltage. This
requirement restricts the number of I/O standards supported
by an I/O bank at any given time.
The number of I/Os which can be used in each I/O bank
depend on the type of I/O standards and the number of VCCIO
and GND pins being used. This restriction is derived from the
electromigration limit of the VCCIO and GND bussing on the
chip. Please refer to the note on page 14 and the application
note titled “Delta39K Family Device I/O Standards and Config-
urations” for details.
I/O Cell
Figure 7 is a block diagram of the Quantum38K I/O cell. The
I/O cell contains a three-state input buffer, an output buffer, and
a register that can be configured as an input or output register.
The output buffer has a slew rate control option that can be
used to configure the output for a slower slew rate. The input
of the device and the pin output can each be configured as
registered or combinatorial; however, only one path can be
configured as registered in a given design.
The output enable can be selected from one of the four global
I/O control signals or from one of two Output Control Channel
(OCC) signals. The output enable can be configured as always
enabled or always disabled or it can be controlled by one of
the remaining inputs to the mux. The selection is done via a
mux that includes VCC and GND as inputs.
I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 7. These global control signals, driven from four
dedicated pins, can only be used as active-high signals and
are available only to the I/O cells thereby implementing fast
resets, register and output enables.
Figure 5. Block Diagram of Channel Memory Block
4096-bit Dual Port
Array
Configurable as
Async/Sync Dual Port
Configurable as
4Kx1, 2Kx2, 1Kx4 and
512x8 block sizes
Horizontal Channel
All channel memory
inputs are driven from
the routing channels
All channel memory outputs
drive dedicated tracks in the
routing channels
GCLK[3:0]
Global Clock
Signals
Ver
tic
al
C
han
nel
Delta39K
bank
0
bank
1
bank
4
bank
5
bank 2
bank 3
bank 6
bank 7
Quantum38K
Figure 6. Quantum38K I/O Bank Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY38100V208-125NTI | 制造商:Cypress Semiconductor 功能描述:CPLD QUANTUM38K 144K GATES 1536 MCRCLLS IND 0.18UM 2.5V/3.3V - Bulk |
| CY3858-000 | 制造商:TE Connectivity 功能描述:2524F0524-1L/9-9-L016 - Cable Rools/Shrink Tubing |
| CY39 | 制造商:PLETRONICS 制造商全稱:Pletronics, Inc. 功能描述:Crystals |
| CY3900I | 功能描述:開發(fā)軟件 ISR Programming Kit RoHS:否 制造商:Atollic Inc. 產(chǎn)品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| CY3900I_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Delta39K⑩⁄Ultra37000⑩ ISR⑩ Programming Kits |
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