參數(shù)資料
型號： CY39200V388-167MGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 8.5 ns, PBGA388
封裝： BGA-388
文件頁數(shù)： 10/57頁
文件大小： 1166K
代理商： CY39200V388-167MGC
PRELIMINARY
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. **
Page 18 of 57
Power-up Sequence Requirements
Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
The part will not start configuration until VCC, VCCIO,
VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached
nominal voltage.
VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG.
All VCCIOs on a bank should be tied to the same potential
and powered up together.
All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
Configuration Parameters
Parameter
Description
Min.
Unit
tRECONFIG
Reconfig pin LOW time before it goes HIGH
200
ns
相關(guān)PDF資料
PDF描述
CY39200V484-167BBC LOADABLE PLD, 8.5 ns, PBGA484
CY39200V676-167MBC LOADABLE PLD, 8.5 ns, PBGA676
CY39200Z208-167NC LOADABLE PLD, 8.5 ns, PQFP208
CY39200Z388-167MGC LOADABLE PLD, 8.5 ns, PBGA388
CY39200Z484-167BBC LOADABLE PLD, 8.5 ns, PBGA484
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200V388-181MGC 制造商:Cypress Semiconductor 功能描述:
CY39200V388-181NC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V388-233MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V388-233MGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V388-233NTC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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