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參數資料
| 型號： | CY7C0832V-167AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120 |
| 文件頁數： | 5/32頁 |
| 文件大?。?/td> | 895K |
| 代理商： | CY7C0832V-167AXC |
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CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 13 of 32
CLAMP
The optional CLAMP instruction allows the state of the signals
driven from CY7C0851V/CY7C0852V pins to be determined
from the boundary-scan register while the BYPASS register is
selected as the serial path between TDI and TDO. CLAMP
controls boundary cells to 1 or 0.
NBSRST
This is the Non-Boundary Scan Reset instruction. NBSRST
places the Bypass Register (BYR) between TDI and TDO
when selected. Its function is to reset every logic (similar to
MRST) except that it does not reset the JTAG logic.
Boundary Scan Cells (BSC)
Every CY7C0851V/CY7C0852V output has two boundary
scan cells; one for data, and one for three-state control. JTAG
TAP pins (TDI, TMS, TDO, TCK), MRST, and all power and
ground pins have no scan cell. Other CY7C0851V/
CY7C0852V inputs have only the data scan cell.
Active and Standby Supply Current[13]
When the instruction in the JTAG instruction register selects
the Boundary Scan Register (BSR) and the TAP controller is
in any state except TEST-LOGIC-RESET or RUN-TEST/IDLE,
then the device supply current (ICC or ISB1/2/3/4) will increase.
With the JTAG logic in this state, and both ports inactive with
CMOS input levels, it is possible for the supply current to
exceed the ISB3 value given in the Electrical Characteristics
section of this data sheet.
Notes:
13. ISB3 values only if JTAG pins are not active and master reset (MRST) not enabled.
14. The “0”/”1” next to each state represents the value at TMS at the rising edge of CLK.
TEST-LOGIC
RESET
RUN_TEST/
IDLE
SELECT
DR-SCAN
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
EXIT2-DR
UPDATE-DR
SELECT
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Figure 3. TAP Controller State Diagram (FSM)[14]
1
[12]
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PDF描述 |
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| CY7C0851AV-133AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-167AXC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0851AV-167BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
| CY7C0852AV-133BBC | FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CY7C0832V-167BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4NS 144FBGA - Bulk |
| CY7C0833AV-100BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 144-Pin FBGA |
| CY7C0833AV-133BBC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 4.7ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述: |
| CY7C0833AV-133BBI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C0833V-100BBC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 9MBIT 512KX18 5NS 144FBGA - Bulk |
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