參數(shù)資料
型號: CY7C0832V-167AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
文件頁數(shù): 19/32頁
文件大小: 895K
代理商: CY7C0832V-167AXC
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 26 of 32
Left_Port (L_Port) Write to Right_Port (R_Port) Read[37, 38, 39]
Notes:
37. CE0 = OE = ADS = CNTEN = B0 – B3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
38. This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data will be Read out.
39. If tCCS < minimum specified value, then R_Port will Read the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock.
If tCCS > minimum specified value, then R_Port will Read the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.
Switching Waveforms (continued)
tSA
tHA
tSW
tHW
tCH2
tCL2
tCYC2
CLKL
R/WL
An
Dn
tCKHZ
tHD
tSA
An
tHA
Qn
tDC
tCCS
tSD
tCKLZ
tCH2
tCL2
tCYC2
tCD2
L_PORT
ADDRESS
L_PORT
DATAIN
CLKR
R/WR
R_PORT
ADDRESS
R_PORT
DATAOUT
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