參數(shù)資料
型號(hào)： CY7C0832V-167AXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
文件頁數(shù)： 21/32頁
文件大?。?/td> 895K
代理商： CY7C0832V-167AXC
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 28 of 32
MailBox Interrupt Timing[45, 46, 47, 48, 49]
Switching Waveforms (continued)
tCH2
tCL2
tCYC2
CLKL
tCH2
tCL2
tCYC2
CLKR
1FFFF
tSA
tHA
An+3
An
An+1
An+2
L_PORT
ADDRESS
Am
Am+4
Am+1
1FFFF
Am+3
R_PORT
ADDRESS
INTR
tSA
tHA
tSINT
tRINT
Table 6. Read/Write and Enable Operation (Any Port)[1, 4, 50, 51, 52]
Inputs
Outputs
Operation
OE
CLK
CE0
CE1
R/W
DQ0 – DQ35
X
H
X
High-Z
Deselected
X
L
X
High-Z
Deselected
XL
H
L
DIN
Write
LL
H
DOUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
Notes:
45. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
46. Address “1FFFF” is the mailbox location for R_Port.
47. L_Port is configured for Write operation, and R_Port is configured for Read operation.
48. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
49. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
50. OE is an asynchronous input signal.
51. When CE changes state, deselection and Read happen after one cycle of latency.
52. CE0 = OE = LOW; CE1 = R/W = HIGH.
相關(guān)PDF資料
PDF描述
CY7C0851AV-133AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-133BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C0832V-167BBC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4NS 144FBGA - Bulk
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CY7C0833AV-133BBI 制造商:Cypress Semiconductor 功能描述:
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