參數(shù)資料
型號(hào)： CY7C1069AV33-10ZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 2M x 8 Static RAM
中文描述： 2M X 8 STANDARD SRAM, 10 ns, PDSO54
封裝： LEAD FREE, TSOP2-54
文件頁(yè)數(shù)： 3/9頁(yè)
文件大?。?/td> 393K
代理商： CY7C1069AV33-10ZXC
CY7C1069AV33
Document #: 38-05255 Rev. *F
Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
CC
to Relative GND
[3]
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
DC Electrical Characteristics
Over the Operating Range
DC Input Voltage
[3]
................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Operating Range
Range
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
Commercial
Industrial
3.3V
±
0.3V
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Leakage Current
Output Leakage Current GND < V
OUT
< V
CC
, Output Disabled
V
CC
Operating
Supply Current
f = f
MAX
= 1/t
RC
Automatic CE
Power-down Current
—TTL Inputs
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Automatic CE
Power-down Current
—CMOS Inputs
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Test Conditions
–10
–12
Unit
V
V
V
V
μ
A
μ
A
mA
Min.
2.4
Max.
Min.
2.4
Max.
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
0.4
0.4
2.0
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
275
2.0
–0.3
–1
–1
V
CC
+ 0.3
0.8
+1
+1
260
GND < V
I
< V
CC
V
CC
= Max.,
I
SB1
CE
2
< V
IL
,
Max. V
CC
, CE
1
> V
IH
70
70
mA
I
SB2
CE
< 0.3V, Max. V
CC
,
CE
1
> V
CC
– 0.3V,
50
50
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
TSOP II
6
8
FBGA
8
10
Unit
pF
pF
T
A
= 25
°
C, f = 1 MHz, V
CC
= 3.3V
AC Test Loads and Waveforms
[5]
Notes:
3. V
(min.) = –2.0V for pulse durations of less than 20 ns.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
90%
10%
3.3V
GND
90%
10%
All input pulses
3.3V
OUTPUT
5 pF*
*Including
jig and
scope
(a)
(b)
R1 317
R2
351
Rise time > 1V/ns
Fall time: > 1V/ns
(c)
OUTPUT
50
Z0= 50
V
TH
= 1.5V
30 pF**Capacitive Load consists of all
components of the test environment
[+] Feedback
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