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參數(shù)資料
| 型號(hào)： | CY7C1069AV33-10ZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2M x 8 Static RAM |
| 中文描述： | 2M X 8 STANDARD SRAM, 10 ns, PDSO54 |
| 封裝： | LEAD FREE, TSOP2-54 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 393K |
| 代理商： | CY7C1069AV33-10ZXC |
CY7C1069AV33
Document #: 38-05255 Rev. *F
Page 4 of 9
AC Switching Characteristics
Over the Operating Range
[7]
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[10, 11]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Description
–10
–12
Unit
Min.
Max.
Min.
Max.
V
CC
(typical) to the First Access
[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW/CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
[9]
OE HIGH to High-Z
[9]
CE
1
LOW/CE
2
HIGH to Low-Z
[9]
CE
1
HIGH/CE
2
LOW to High-Z
[9]
CE
1
LOW/CE
2
HIGH to Power-up
[10]
CE
1
HIGH/CE
2
LOW to Power-down
[10]
1
1
12
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
12
3
3
10
5
12
6
1
1
5
6
3
3
5
6
0
0
10
12
Write Cycle Time
CE
1
LOW/CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[9]
WE LOW to High-Z
[9]
10
7
7
0
0
7
5.5
0
3
12
8
8
0
0
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
6
Data Retention Waveform
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
, normal SRAM operation can begin including reduction in V
to the data retention (V
, 2.0V) voltage.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a Read/Write operation is
started.
9. t
, t
, t
and t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
200 mV from
steady-state voltage.
10.These parameters are guaranteed by design and are not tested.
11.The internal Write time of the memory is defined by the overlap of
CE
LOW/CE
HIGH
, and WE LOW. CE
and WE must be LOW along with CE
HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
12.The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
3.0V
3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
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| CY7C1069AV33-10ZXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 8 CPG COM Fast Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1069AV33-10ZXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 8 CPG IND Fast Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1069AV33-10ZXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2M x 8 CPG IND Fast Async 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1069AV33-12ZC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY7C1069AV33-12ZI | 制造商:Cypress Semiconductor 功能描述: |
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