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參數(shù)資料
| 型號： | CY7C106 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 4 Static RAM(256K x 4 靜態(tài) RAM) |
| 中文描述： | 256K × 4靜態(tài)存儲器（256K × 4靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 203K |
| 代理商： | CY7C106 |
256K x 4 Static RAM
CY7C106
CY7C1006
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 9, 1998
Features
High speed
—t
AA
=
12 ns
CMOS for optimum speed/power
Low active power
—910 mW
Low standby power
—275 mW
2.0V data retention (optional)
—
100
μ
W
Automatic power-down when deselected
TTL-compatible inputs and outputs
Functional Description
The CY7C106 and CY7C1006 are high-performance CMOS
static RAMs organized as 262,144 words by 4 bits. Easy mem-
ory expansion is provided by an active LOW chip enable (CE),
an active LOW output enable (OE), and three-state drivers.
These devices have an automatic power-down feature that re-
duces power consumption by more than 65% when the devic-
es are deselected.
Writing to the devices is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. Data on the four I/O
pins (I/O
0
through I/O
3
) is then written into the location speci-
fied on the address pins (A
0
through A
17
).
Reading from the devices is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing write en-
able (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the four I/O pins.
The four input/output pins (I/O
0
through I/O
3
) are placed in a
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106 is available in a standard 400-mil-wide SOJ; the
CY7C1006 is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
C106–1
C106–2
512 x 512 x 4
ARRAY
A
1
A
2
A
3
A
4
A
5
A
0
A
1
A
1
A
1
A
1
A
1
COLUMN
DECODER
R
S
POWER
DOWN
OE
INPUTBUFFER
A
1
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
21
24
23
22
Top View
SOJ
25
28
27
26
GND
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
CE
OE
A
17
A
16
A
15
A
14
A
13
A
12
A
11
V
CC
I/O
3
I/O
2
I/O
1
I/O
0
WE
A
0
NC
WE
CE
I/O
0
I/O
1
I/O
2
I/O
3
A
6
A
7
A
8
A
9
Selection Guide
7C106-12
7C1006-12
12
165
7C106-15
7C1006-15
15
155
7C106-20
7C1006-20
20
145
7C106-25
7C1006-25
25
130
7C106-35
35
125
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
50
30
30
30
25
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