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參數(shù)資料
| 型號： | CY7C1215H-100AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| 中文描述： | 32K X 32 CACHE SRAM, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 380K |
| 代理商： | CY7C1215H-100AXC |
CY7C1215H
Document #: 38-05666 Rev. *B
Page 5 of 15
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
Truth Table[2, 3, 4, 5, 6]
Next Cycle
Add. Used
ZZ
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
H
X
L
X
Tri-State
X
Unselected
None
L
X
H
L
X
Tri-State
X
Unselected
None
L
X
L
X
Tri-State
X
Unselected
None
L
X
H
L
X
Tri-State
X
Unselected
None
L
X
H
L
X
Tri-State
X
Begin Read
External
L
H
L
X
Tri-State
X
Begin Read
External
L
H
L
H
L
X
Tri-State
Read
Continue Read
Next
L
X
H
L
H
Tri-State
Read
Continue Read
Next
L
X
H
L
DQ
Read
Continue Read
Next
L
H
X
H
L
H
Tri-State
Read
Continue Read
Next
L
H
X
H
L
DQ
Read
Suspend Read
Current
L
X
H
Tri-State
Read
Suspend Read
Current
L
X
H
L
DQ
Read
Suspend Read
Current
L
H
X
H
Tri-State
Read
Suspend Read
Current
L
H
X
H
L
DQ
Read
Begin Write
Current
L
X
H
X
Tri-State
Write
Begin Write
Current
L
H
X
H
X
Tri-State
Write
Begin Write
External
L
H
L
H
X
Tri-State
Write
Continue Write
Next
L
X
H
X
Tri-State
Write
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
(BWA,BWB,BWC,BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
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