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參數(shù)資料
| 型號： | CY7C1215H-100AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 1-Mbit (32K x 32) Pipelined Sync SRAM |
| 中文描述： | 32K X 32 CACHE SRAM, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 380K |
| 代理商： | CY7C1215H-100AXC |
CY7C1215H
Document #: 38-05666 Rev. *B
Page 3 of 15
Pin Definitions
Name
I/O
Description
A0, A1, A
Input-
Synchronous
Address Inputs used to select one of the 32K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0
feed the 2-bit counter.
BWA, BWB
BWC, BWD
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is
loaded.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device. Not connected for BGA. Where referenced, CE3 is
assumed active throughout this document for BGA. CE3 is sampled only when a new external
address is loaded.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a Read cycle when emerging from a
deselected state.
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1
is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ “Sleep” Input, active HIGH. This input, when HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
DQs
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by “A” during the previous clock rise of the Read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ are
placed in a tri-state condition.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
VSSQ
I/O Ground
Ground for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC
No Connects. Not internally connected to the die. 2M, 4M, 9M, 18M, 72M, 144M, 288M, 576M
and 1G are address expansion pins and are not internally connected to the die.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1215H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1MBIT 32KX32 3.5NS 100TQFP - Bulk |
| CY7C1217H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC QUAD 3.3V 1.125MBIT 32KX36 7.5NS 100TQFP - Bulk |
| CY7C1218H-133AXC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1218H-166AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 1.125MBIT 32KX36 3.5NS 100TQFP - Bulk |
| CY7C1219F-133AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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