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參數(shù)資料
| 型號(hào)： | CY7C133-55JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K x 16 Dual-Port Static RAM |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 55 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 506K |
| 代理商： | CY7C133-55JI |
2K x 16 Dual-Port Static RAM
CY7C133
CY7C143
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-06036 Rev. *B
Revised June 22, 2004
Features
True dual-ported memory cells which allow
simultaneous reads of the same memory location
2K x 16 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 25/35/55 ns
Low operating power: I
CC
= 150 mA (typ.)
Fully asynchronous operation
Master CY7C133 expands data bus width to 32 bits or
more using slave CY7C143
BUSY output flag on CY7C133; BUSY input flag on
CY7C143
Available in 68-pin PLCC
Functional Description
The CY7C133 and CY7C143 are high-speed CMOS 2K by 16
dual-port static RAMs. Two ports are provided permitting
independent access to any location in memory. The CY7C133
can be utilized as either a stand-alone 16-bit dual-port static
RAM or as a master dual-port RAM in conjunction with the
CY7C143 slave dual-port device in systems requiring 32-bit or
greater word widths. It is the solution to applications requiring
shared or buffered data, such as cache memory for DSP,
bit-slice, or multiprocessor designs.
Each port has independent control pins; Chip Enable (CE),
Write Enable (R/W
UB
, R/W
LB
), and Output Enable (OE).
BUSY signals that the port is trying to access the same
location currently being accessed by the other port. An
automatic power-down feature is controlled independently on
each port by the Chip Enable (CE) pin.
The CY7C133 and CY7C143 are available in 68-pin PLCC.
Note:
1.
CY7C133 (Master): BUSY is open drain output and requires pull-up resistor. CY7C143 (Slave): BUSY is input.
R/W
LUB
CE
L
OE
L
A
10L
A
0L
R/W
RUB
CE
R
CE
R
OE
R
R/W
RUB
R/W
RLB
CE
L
OE
L
R/W
LUB
R/W
LLB
I/O
8L
– I/O
15L
ARBITRATION
LOGIC
(CY7C133ONLY)
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
BUSY
L[1]
CONTROL
I/O
I/O
0L
– I/O
7L
R/W
RLB
OE
R
A
10R
A
0R
I/O
8R
– I/O
15R
BUSY
R
[ ]
1
I/O
0R
– I/O
7R
R/W
LLB
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C143 | 2K x 16 Dual-Port Static RAM |
| CY7C143-25JC | 2K x 16 Dual-Port Static RAM |
| CY7C143-25JI | 2K x 16 Dual-Port Static RAM |
| CY7C143-35JC | 2K x 16 Dual-Port Static RAM |
| CY7C143-35JI | 2K x 16 Dual-Port Static RAM |
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