參數(shù)資料
型號(hào): CY7C133-55JI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2K x 16 Dual-Port Static RAM
中文描述: 2K X 16 DUAL-PORT SRAM, 55 ns, PQCC68
封裝: PLASTIC, LCC-68
文件頁(yè)數(shù): 9/13頁(yè)
文件大?。?/td> 506K
代理商: CY7C133-55JI
CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 9 of 13
Timing Waveform of Read with Port-to-port Delay No. 4 (for slave CY7C143)
[24, 25, 26]
Write Cycle No. 1 (OE Three-States Data I/Os - Either Port)
[17, 27]
Notes:
24. Assume BUSY input at V
for the writing port and at V
for the reading port.l
25. Write cycle parameters should be adhered to in order to ensure proper writing.
26. Device is continuously enabled for both ports.
27. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high
impedance and for data to be placed on the bus for the required t
SD
.
Switching Waveforms
(continued)
VALID
t
DDD
MATCH
MATCH
R/W
R
D
INR
DOUT
L
t
WC
t
WP
VALID
t
WDD
t
DH
t
DW
ADDRESS
L
ADDRESS
R
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
EitherPort
R/W
CE
ADDRESS
DATA
IN
OE
D
OUT
相關(guān)PDF資料
PDF描述
CY7C143 2K x 16 Dual-Port Static RAM
CY7C143-25JC 2K x 16 Dual-Port Static RAM
CY7C143-25JI 2K x 16 Dual-Port Static RAM
CY7C143-35JC 2K x 16 Dual-Port Static RAM
CY7C143-35JI 2K x 16 Dual-Port Static RAM
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