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參數(shù)資料
| 型號： | CY7C133-55JI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K x 16 Dual-Port Static RAM |
| 中文描述： | 2K X 16 DUAL-PORT SRAM, 55 ns, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 506K |
| 代理商： | CY7C133-55JI |
CY7C133
CY7C143
Document #: 38-06036 Rev. *B
Page 3 of 13
Architecture
The CY7C133 (master) and CY7C143 (slave) consist of an
array of 2K words of 16 bits each of dual-port RAM cells, I/O
and address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to any
location in memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. The CY7C133 and
CY7C143 have an automatic power-down feature controlled by CE.
Each port is provided with its own output enable control (OE), which
allows data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of t
SD
before the rising edge
of R/W in order to guarantee a valid write. A write operation is
controlled by either the R/W pin (see Write Cycle No. 1 waveform) or
the CE pin (see Write Cycle No. 2 waveform). Two R/W pins (R/W
UB
and R/W
LB
) are used to separate the upper and lower bytes of IO.
Required inputs for non-contention operations are summarized in
Table 1
.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flow-through
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after OE is
asserted.
Busy
The CY7C133 (master) provides on-chip arbitration to resolve
simultaneous memory location access (contention).
Table 2
shows a summery of conditions where BUSY is asserted. If both
ports’ CEs are asserted and an address match occurs within t
PS
of
each other, the busy logic will determine which port has access. If t
PS
is violated, one port will definitely gain permission to the location, but
which one is not predictable. BUSY will be asserted t
BLA
after an
address match or t
BLC
after CE is taken LOW. The results of all eight
arbitration possibilities are summarized in
Table 3
. BUSY is an open
drain output and requires a pull-up resistor.
One master and as many slaves as necessary may be
connected in parallel to expand the data bus width in 16 bit
increments. The BUSY output of the master is connected to the
BUSY input of the slave. Writing to slave devices must be delayed
until after the BUSY input has settled (t
BLC
or t
BLA
). Otherwise, the
slave chip may begin a write cycle during a contention
situation.
Flow-Through Operation
The CY7C133/143 has a flow-through architecture that facili-
tates repeating (actually extending) an operation when a
BUSY is received by a losing port. The BUSY signal should be
interpreted as a NOT READY. If a BUSY to a port is active, the
port should wait for BUSY to go inactive, and then extend the
operation it was performing for another cycle. The timing
diagram titled, “Timing waveform with port to port delay” illus-
trates the case where the right port is writing to an address and
the left port reads the same address. The data that the right
port has just written flows through to the left, and is valid either
t
DDD
after the falling edge of the write strobe of the left port, or
t
DDD
after the data being written becomes stable.
Data Retention Mode
The CY7C133/143 is designed with battery backup in mind.
Data retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE) must be held HIGH during data retention, with-
in V
CC
to V
CC
– 0.2V.
2. CE must be kept between V
CC
– 0.2V and 70% of V
CC
during the power-up and power-down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (4.5V).
Note:
2.
CE = V
CC
, V
in
= GND to V
CC
, T
A
= 25°C. This parameter is guaranteed but not tested.
Timing
Parameter
ICC
DR1
Test Conditions
[2]
@ VCC
DR
= 2V
Max.
1.5
Unit
mA
Data Retention Mode
4.5V
4.5V
V
CC
>
2.0V
V
CC
to V
CC
– 0.2V
V
CC
CE
t
RC
VIH
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相關(guān)代理商/技術(shù)參數(shù) |
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