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參數(shù)資料
| 型號： | CY7C1332 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 18 Synchronous Cache 3.3V RAM(3.3V 64K x 18 同步高速緩沖存儲器 RAM) |
| 中文描述： | 64K的× 18同步高速緩存3.3V的內(nèi)存電壓（3.3V 64K的× 18同步高速緩沖存儲器的RAM） |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 313K |
| 代理商： | CY7C1332 |
CY7C1331
CY7C1332
ADVANCED INFORMATION
3
Pin Definitions
Signal Name
Type
# of Pins
Description
V
CC
V
CCQ
GND
Input
1
+
3.3V Power
+
3.3V (Outputs)
Ground
Input
4
Input
1
V
SSQ
CLK
Input
4
Ground (Outputs)
Input
1
Clock
A
15
– A
0
ADSP
Input
16
Address
Input
1
Address Strobe from Processor
ADSC
Input
1
Address Strobe from Cache Controller
WH
Input
1
Write Enable – High Byte
WL
Input
1
Write Enable – Low Byte
ADV
Input
1
Advance
OE
Input
1
Output Enable
CS
Input
1
Chip Select
DQ
15
–DQ
0
DP
1
–DP
0
Pin Descriptions
Input/Output
16
Regular Data
Input/Output
2
Parity Data
Pin Descriptions
(continued)
Signal
Name
I/O
Description
CLK
I
Clock signal. It is used to capture the ad-
dress, the data to be written, and the fol-
lowing control signals: ADSP ADSC, WH,
WL, CS, and ADV. It is also used to ad-
vance the on-chip auto-address-increment
logic (when the appropriate control signals
have been set).
A
15
-A
0
I
Sixteen address lines used to select one of
64K locations. They are captured in an
on-chip register on the rising edge of CLK
if ADSP or ADSC is LOW. The rising edge
of the clock also loads the lower two ad-
dress lines, A
1
- A
0
, into the on-chip au-
to-address-increment logic if ADSP or
ADSC is LOW.
ADSP
I
Address strobe from processor. This signal
is sampled at the rising edge of CLK. When
this input and/or ADSC is asserted, A
0
-A
15
will be captured in the on-chip address reg-
ister. It also allows the lower two address
bits to be loaded into the on-chip auto-ad-
dress-increment logic. If both ADSP and
ADSC are asserted at the rising edge of
CLK, only ADSP will be recognized. The
ADSP input should be connected to the
ADS output of the processor. ADSP is ig-
nored when CS is HIGH.
ADSC
I
Address strobe from cache controller. This
signal is sampled at the rising edge of CLK.
When this input and/or ADSP is asserted,
A
0
-A
15
will be captured in the on-chip ad-
dress register. It also allows the lower two
address bits to be loaded into the on-chip
auto-address-increment logic. The ADSC
input should not be connected to the ADS
output of the processor.
WH
I
Write signal for the high-order half of the
RAM array. This signal is sampled by the
rising edge of CLK. If WH is sampled as
LOW, i.e., asserted, the control logic will
perform a self-timed write of DQ
15
- DQ
8
and DP
1
from the on-chip data register into
the selected RAM location. There is one
exception to this. If ADSP, WH, and CS are
asserted (LOW) at the rising edge of CLK,
the write signal, WH, is ignored. Note that
ADSP has no effect onWH if CS is HIGH.
WL
I
Write signal for the low-order half of the
RAM array. This signal is sampled by the
rising edge of CLK. If WL is sampled as
LOW, i.e., asserted, the control logic will
perform a self-timed write of DQ
7
- DQ
0
and DP
0
from the on-chip data register into
the selected RAM location. There is one
exception to this. If ADSP ,WL, and CS are
asserted (LOW) at the rising edge of CLK,
the write signal, WL, is ignored. Note that
ADSP has no effect on WL if CS is HIGH.
Signal
Name
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1331 | 64K x 18 Synchronous Cache 3.3V RAM(3.3V 64K x 18 同步高速緩沖存儲器 RAM) |
| CY7C1333 | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| CY7C1334 | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| CY7C1335 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM) |
| CY7C1336 | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C133-25JC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 2Kx16, 68 Pin, Plastic, LDCC |
| CY7C1332AV25-200BGC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1333-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C133-35JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 35ns 68-Pin PLCC |
| CY7C1333-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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