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參數(shù)資料
| 型號(hào)： | CY7C1332 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 18 Synchronous Cache 3.3V RAM(3.3V 64K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| 中文描述： | 64K的× 18同步高速緩存3.3V的內(nèi)存電壓（3.3V 64K的× 18同步高速緩沖存儲(chǔ)器的RAM） |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大?。?/td> | 313K |
| 代理商： | CY7C1332 |
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CY7C1331
CY7C1332
ADVANCED INFORMATION
4
ADV
I
Advance. This signal is sampled by the ris-
ing edge of CLK. When it is asserted, it
automatically increments the two-bit
on-chip auto-address-increment counter.
In the CY7C1332, the address will be in-
cremented linearly. In the CY7C1331, the
address will be incremented according to
the Pentium/486 burst sequence. This sig-
nal is ignored if ADSP or ADSC is asserted
concurrently with CS. Note that ADSP has
no effect on ADV if CS is HIGH.
CS
I
Chip select. This signal is sampled by the
rising edge of CLK. If CS is HIGH and
ADSC is LOW, the SRAM is deselected. If
CS is LOW and ADSC or ADSP is LOW, a
new address is captured by the address
register. If CS is HIGH, ADSP is ignored.
OE
I
Output enable. This signal is an asynchro-
nous input that controls the direction of the
data I/O pins. If OE is asserted (LOW), the
data pins are outputs, and the SRAM can
be read (as long as CS was asserted when
it was sampled at the beginning of the cy-
cle). If OE is deasserted (HIGH), the data
I/O pins will be three-stated, functioning as
inputs, and the SRAM can be written.
Pin Descriptions
(continued)
Signal
Name
I/O
Description
Bidirectional Signals
DQ
15
-DQ
0
I/O
Sixteen bidirectional data I/O lines. DQ
15
-
DQ
8
are inputs to and outputs from the
high-order half of the RAM array, while DQ
7
- DQ
0
are inputs to and outputs from the
low-order half of the RAM array. As inputs,
they feed into an on-chip data register that
is triggered by the rising edge of CLK. As
outputs, they carry the data read from the
selected location in the RAM array. The di-
rection of the data pins is controlled by OE:
when OE is high, the data pins are
three-stated and can be used as inputs;
when OE is low, the data pins are driven by
the output buffers and are outputs. DQ
15
-
DQ
8
and DQ
7
- DQ
0
are also three-stated
when WH and WL, respectively, are sam-
pled LOW at clock rise.
DP
1
-DP
0
I/O
Two bidirectional data I/O lines. These op-
erate in exactly the same manner as DQ
15
- DQ
0
, but are named differently because
their primary purpose is to store parity bits,
while the DQs’ primary purpose is to store
ordinary data bits. DP
1
is an input to and
an output from the high-order half of the
RAM array, while DP
0
is an input to and an
output from the lower-order half of the RAM
array.
Pin Descriptions
(continued)
Signal
Name
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1331 | 64K x 18 Synchronous Cache 3.3V RAM(3.3V 64K x 18 同步高速緩沖存儲(chǔ)器 RAM) |
| CY7C1333 | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| CY7C1334 | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| CY7C1335 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| CY7C1336 | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C133-25JC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 2Kx16, 68 Pin, Plastic, LDCC |
| CY7C1332AV25-200BGC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1333-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C133-35JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 35ns 68-Pin PLCC |
| CY7C1333-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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