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參數(shù)資料
| 型號(hào)： | CY7C1335 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| 中文描述： | 32K的× 32同步流水線緩存內(nèi)存（32K的× 32同步流水線式高速緩沖存儲(chǔ)器的RAM） |
| 文件頁(yè)數(shù)： | 1/15頁(yè) |
| 文件大小： | 278K |
| 代理商： | CY7C1335 |
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32K x 32 Synchronous-Pipelined Cache RAM
CY7C1335
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
July 30, 1999
aven’t
re
2CY7C1329
Features
Supports 100-MHz bus for Pentium
and PowerPC
operations with zero wait states
Fully registered inputs and outputs for pipelined
operation
32K by 32 common I/O architecture
Single 3.3V power supply
Fast clock-to-output times
—4.2 ns (for 133-MHz device)
—5.5 ns (for 100-MHz device)
—7.0 ns (for 75-MHz device
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1335 is a 3.3V, 32K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 4.2 ns (133-MHz
device).
The CY7C1335 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW
[3:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
ADSP
A
[14:0]
GW
BWE
BW
3
BW
2
BW
1
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
DQ[31:24]
ADDRESS
REGISTER
D
Q
ROUTPUT
CLK
INPUT
REGISTERS
CLK
32KX32
MEMORY
ARRAY
Q
0
Q
1
Q
D
CLR
SLEEP
DQ[23:16]
D
Q
D
Q
DQ[15:8]
BDQ[7:0]
D
Q
ENABLE
REGISTER
CLK
D
CE
Q
ENREGISTER
CLK
D
Q
32
32
15
13
13
15
(A
[1;0]
)
2
MODE
DQ
[31:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1336 | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| CY7C1337 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| CY7C1338G-117AXI | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
| CY7C1338G-133BGXI | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
| CY7C1338G-100AXC | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C133-55JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 55ns 68-Pin PLCC |
| CY7C1335-75AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1336F-117AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 7.5ns 100-Pin TQFP |
| CY7C1336H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 64KX32 6.5NS 100TQFP - Bulk |
| CY7C1338B-100AC | 功能描述:IC SRAM 4MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán) |
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