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參數(shù)資料
| 型號： | CY7C1333 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| 中文描述： | 64Kx32流過式的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的64Kx32流通式的SRAM） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CY7C1333 |
CY7C1333
3
Pin Definitions
Pin Number
49
44,
81
–
82, 99,
100, 32
–
37
96
–
93
Name
A
[15:0]
I/O
Input-
Synchronous
Description
Address Inputs used to select one of the 65,536 address locations. Sampled at the
rising edge of the CLK.
BWS
[3:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS
0
controls DQ
[7:0]
, BWS
1
controls
DQ
[15:8]
, BWS
2
controls DQ
[23:16]
, BWS
0
controls DQ
[31:24]
.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state, when the device has
been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
the deasserting CEN does not deselect the device, CEN can be used to extend
the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[15:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
[31:0]
are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating Mode will default HIGH, to an interleaved
burst order.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
88
WE
Input-
Synchronous
Input-
Synchronous
85
ADV/LD
89
CLK
Input-Clock
98
CE
1
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
97
CE
2
92
CE
3
86
OE
87
CEN
Input-
Synchronous
29
–
28,25
–
22,
19
–
18,13
–
12,
9
–
6, 3
–
2,
79
–
78,75
–
72,
69
–
68,63
–
62
59
–
56,53
–
52
DQ
[31:0]
I/O-
Synchronous
31
Mode
Input
Strap pin
15, 16, 41, 65,
91
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 14, 21,
26, 55, 60, 66,
71, 76
64
V
DD
Power Supply
V
SS
V
DDQ
Ground
I/O Power
Supply
I/O Ground
V
SSQ
Ground for the I/O circuitry. Should be connected to ground of the system.
NC
-
No Connect. Reserved for drive strength control input.
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