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參數(shù)資料
| 型號： | CY7C1333 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| 中文描述： | 64Kx32流過式的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的64Kx32流通式的SRAM） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CY7C1333 |
CY7C1333
6
Write Cycle Description
[7, 8]
Function
WE
BWS
3
X
BWS
2
X
BWS
1
X
BWS
0
X
Read
1
Write - No bytes written
0
1
1
1
1
Write Byte 0 - DQ
[7:0]
Write Byte 1 - DQ
[15:8]
Write Bytes 1, 0
0
1
1
1
0
0
1
1
0
1
0
1
1
0
0
Write Byte 2 - DQ
[23:16]
Write Bytes 2, 0
0
1
0
1
1
0
1
0
1
0
Write Bytes 2, 1
0
1
0
0
1
Write Bytes 2, 1, 0
0
1
0
0
0
Write Byte 3 - DQ
[31:24]
Write Bytes 3, 0
0
0
1
1
1
0
0
1
1
0
Write Bytes 3, 1
0
0
1
0
1
Write Bytes 3, 1, 0
0
0
1
0
0
Write Bytes 3, 2
0
0
0
1
1
Write Bytes 3, 2, 0
0
0
0
1
0
Write Bytes 3, 2, 1
0
0
0
0
1
Write All Bytes
0
0
0
0
0
Notes:
7.
8.
X=
”
Don
’
t Care
”
, 1=Logic HIGH, 0=Logic LOW.
Write is initiated by the combination of WE and BWS
x
. Bytes written are determined by BWS
[3:0]
. Bytes not selected during byte writes remain unaltered. All
I/Os are three-stated during byte writes.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1334 | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| CY7C1335 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM) |
| CY7C1336 | 64K x 32 Synchronous Flow-Through 3.3V Cache RAM(3.3V 64K x 32 同步流通式高速緩沖RAM) |
| CY7C1337 | 32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水線式高速緩沖存儲器 RAM) |
| CY7C1338G-117AXI | 4-Mbit (128K x 32) Flow-Through Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1333-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C133-35JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 35ns 68-Pin PLCC |
| CY7C1333-66AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1333H-133AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 3.3V 2MBIT 64KX32 6.5NS 100TQFP - Bulk |
| CY7C1334-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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