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參數(shù)資料
| 型號： | CY7C1334 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64Kx32 Flow-Thru SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的64Kx32流通式 SRAM) |
| 中文描述： | 64Kx32流過式的SRAM架構(gòu)的總線延遲（帶總線延遲結(jié)構(gòu)的64Kx32流通式的SRAM） |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 184K |
| 代理商： | CY7C1334 |
CY7C1334
8
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
Notes
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
Θ
JA
28
°
C/W
13
Thermal Resistance
(Junction to Case)
Θ
JC
4
°
C/W
13
Switching Characteristics
Over the Operating Range
[14, 15, 16]
-133
-100
-80
-50
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
CYC
Clock Cycle Time
7.5
10
12.5
20.0
ns
t
CH
Clock HIGH
2.2
3.5
4.0
6.0
ns
t
CL
Clock LOW
2.2
3.5
4.0
6.0
ns
t
CO
Data Output Valid After CLK Rise
4.2
5.0
7.0
10.0
ns
t
DOH
Data Output Hold After CLK Rise
1.5
1.5
1.5
1.5
ns
t
AS
Address Set-Up Before CLK Rise
2.0
2.2
2.5
3.0
ns
t
AH
Address Hold After CLK Rise
0.5
0.5
1.0
1.5
ns
t
CENS
CEN Set-Up Before CLK Rise
2.0
2.2
2.5
3.0
ns
t
CENH
CEN Hold After CLK Rise
0.5
0.5
1.0
1.5
ns
t
WES
GW, BWS
[3:0]
Set-Up Before CLK Rise
2.0
2.2
2.5
3.0
ns
t
WEH
GW, BWS
[3:0]
Hold After CLK Rise
0.5
0.5
1.0
1.5
ns
t
ALS
ADV/LD Set-Up Before CLK Rise
2.0
2.2
2.5
3.0
ns
t
ALH
ADV/LD Hold after CLK Rise
0.5
0.5
1.0
1.5
ns
t
DS
Data Input Set-Up Before CLK Rise
1.7
2.0
2.5
3.0
ns
t
DH
Data Input Hold After CLK Rise
0.5
0.5
1.0
1.5
ns
t
CES
Chip Enable Set-Up Before CLK Rise
2.0
2.2
2.5
3.0
ns
t
CEH
Chip Enable Hold After CLK Rise
0.5
0.5
1.0
1.5
ns
t
CHZ
Clock to High-Z
[13, 15, 16, 17]
1.5
3.5
1.5
3.5
1.5
3.5
1.5
3.5
ns
t
CLZ
Clock to Low-Z
[13, 15, 16, 17]
1.5
1.5
1.5
1.5
ns
t
EOHZ
OE HIGH to Output High-Z
[13, 15, 16, 17]
4.2
5.0
6.0
6.0
ns
t
EOLZ
OE LOW to Output Low-Z
[13, 15, 16, 17]
OE LOW to Output Valid
[15]
1.0
1.0
1.0
1.0
ns
t
EOV
4.2
5.0
6.0
6.0
ns
Notes:
15. t
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured
±
200 mV from steady-state
voltage.
16. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
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參數(shù)描述 |
|---|---|
| CY7C1334-50AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY7C1334-80AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1334H-166AXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 64Kx32 3.3V NoBL Sync PL 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C133-55JC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Dual 5V 32K-Bit 2K x 16 55ns 68-Pin PLCC |
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