- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378502 > CY7C1381C-100AC (CYPRESS SEMICONDUCTOR CORP) 18-Mb (512K x 36/1M x 18) Flow-Through SRAM PDF資料下載
參數(shù)資料
| 型號： | CY7C1381C-100AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 8.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 7/36頁 |
| 文件大小： | 564K |
| 代理商： | CY7C1381C-100AC |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
CY7C1381C
CY7C1383C
Document #: 38-05238 Rev. *B
Page 7 of 36
ADSC
85
B4
A8
Input-
Synchronous
Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented
to the device are captured in the address
registers. A
[1:0]
are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
BWE
87
M4
A7
Input-
Synchronous
Byte Write Enable Input, active LOW
.
Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a
byte write.
ZZ
64
T7
H11
Input-
Asynchronous
ZZ “sleep” Input, active HIGH
. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
DQ
s
52,53,56,57,58,
59,62,63,68,69,
72,73,74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22,
23,24,25,28,29
K6,L6,M6,N6,K7
,L7,N7,P7,E6,F
6,G6,H6,D7,E7,
G7,H7,D1,E1,G
1,H1,E2,F2,G2,
H2,K1,L1,N1,P1
,K2,L2,M2,N2
M11,L11,K11,
J11,J10,K10,
L10,M10,D10,
E10,F10,G10,
D11,E11,F11,
G11,D1,E1,
F1,G1,D2,E2,
F2,G2,J1,K1,
L1,M1,J2,
K2,L2,M2,
I/O-
Synchronous
Bidirectional Data I/O lines
. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As
outputs, they deliver the data contained in
the memory location specified by the
addresses presented during the previous
clock rise of the read cycle. The direction of
the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs.
When HIGH, DQ
and DQP
are placed
in a tri-state condition.The outputs are
automatically tri-stated during the data
portion of a write sequence, during the first
clock when emerging from a deselected
state, and when the device is deselected,
regardless of the state of OE.
DQP
[A:D]
51,80,1,30
P6,D6,D2,P2
N11,C11,C1,N1
I/O-
Synchronous
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQ
s
.
During write sequences, DQP
[A:D]
is
controlled by BW
[A:D]
correspondingly.
MODE
31
R3
R1
Input-Static
Selects Burst Order
. When tied to GND
selects linear burst sequence. When tied to
V
DD
or left floating selects interleaved burst
sequence. This is a strap pin and should
remain static during device operation. Mode
Pin has an internal pull-up.
V
DD
15,41,65,91
J2,C4,J4,R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
Power Supply
Power supply inputs to the core of the
device
.
CY7C1381C–Pin Definitions
(continued)
Name
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1381C-100AI | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383C-133AC | CAP .22UF 50V POLY B SERIES |
| CY7C1383C-133BGC | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381D_07 | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381D-133AXI | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1381C-100BGC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-FT SRAM - Bulk |
| CY7C1381C-100BGCT | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1381C-100BGI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381C-100BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381C-100BZI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-FT SRAM - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。