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參數(shù)資料
| 型號： | CY7C1381C-100AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| 中文描述： | 512K X 36 STANDARD SRAM, 8.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 8/36頁 |
| 文件大?。?/td> | 564K |
| 代理商： | CY7C1381C-100AC |
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CY7C1381C
CY7C1383C
Document #: 38-05238 Rev. *B
Page 8 of 36
V
DDQ
4,11,20,27,
54,61,70,77
A1,F1,J1,M1,U1
,
A7,F7,J7,M7,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
I/O Power
Supply
Power supply for the I/O circuitry
.
V
SS
17,40,67,90
H2,D3,E3,F3,H3
,K3,
M3,N3,
P3,D5,E5,F5,H5
,K5,
M5,N5,P5
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,K7,
L5,L6,L7,M5,M6
,M7,N4,N8
Ground
Ground for the core of the device
.
V
SSQ
5,10,21,26,
55,60,71,76
-
-
I/O Ground
Ground for the I/O circuitry
.
TDO
-
U5
P7
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit
.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
TDI
-
U3
P5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit
. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left
floating or connected to V
DD
through a pull
up resistor. This pin is not available on TQFP
packages.
TMS
-
U2
R5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit
. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon-
nected or connected to V
DD
. This pin is not
available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry
. If the
JTAG feature is not being utilized, this pin
must be connected to V
SS
. This pin is not
available on TQFP packages.
NC
16,38,39,66
B1,C1,R1,T1,T2
,J3,D4,L4,J5,R5
,T6,U6,B7,C7,R
7
A1,A11,B1,
B11,C2,C10,H1,
H3,H9,
H10,N2,N5,N7,
N10,P1,P2,R2
-
No Connects
. Not internally connected to
the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.
V
SS
/DNU
14
-
-
Ground/DNU This pin can be connected to Ground or
should be left floating.
CY7C1381C–Pin Definitions
(continued)
Name
TQFP
(3-Chip
Enable)
BGA
(1-Chip
Enable)
fBGA
(3-Chip
Enable)
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1381C-100AI | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1383C-133AC | CAP .22UF 50V POLY B SERIES |
| CY7C1383C-133BGC | 18-Mb (512K x 36/1M x 18) Flow-Through SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1381C-100BGC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-FT SRAM - Bulk |
| CY7C1381C-100BGCT | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1381C-100BGI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381C-100BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1381C-100BZI | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V SYNC-FT SRAM - Bulk |
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