參數(shù)資料
型號： CY7C1387DV25-225BZI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
封裝： 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
文件頁數(shù)： 14/32頁
文件大?。?/td> 501K
代理商： CY7C1387DV25-225BZI
PRELIMINARY
CY7C1386DV25
CY7C1387DV25
Document #: 38-05548 Rev. **
Page 21 of 32
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°C to +150°C
Ambient Temperature with
Power Applied.............................................–55
°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature
VDD
VDDQ
Commercial
0°C to +70°C
2.5V + 5%
2.5V– 5%
to VDD
Industrial
–40°C to +85°C
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
2.375
2.625
V
VDDQ
I/O Supply Voltage
VDDQ = 2.5V
2.375
VDD
V
VOH
Output HIGH Voltage
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
2.0
V
VOL
Output LOW Voltage
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
0.4
V
VIH
Input HIGH Voltage[13]
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VIL
Input LOW Voltage[13]
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
except ZZ and MODE
GND
≤ VI ≤ VDDQ
–5
5
A
Input Current of MODE Input = VSS
–5
A
Input = VDD
30
A
Input Current of ZZ
Input = VSS
–30
A
Input = VDD
5
A
IOZ
Output Leakage Current GND
≤ VI ≤ VDDQ, Output Disabled
–5
5
A
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
350
mA
4.4-ns cycle, 225 MHz
325
mA
5-ns cycle, 200 MHz
300
mA
6-ns cycle, 167 MHz
275
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
160
mA
4.4-ns cycle, 225 MHz
TBD
mA
5-ns cycle, 200 MHz
150
mA
6-ns cycle, 167 MHz
140
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
All speeds
70
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
VDD = Max, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
4.0-ns cycle, 250 MHz
135
mA
4.4-ns cycle, 225 MHz
TBD
mA
5-ns cycle, 200 MHz
130
mA
6-ns cycle, 167 MHz
125
mA
ISB4
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All Speeds
80
mA
Shaded areas contain advance information.
Notes:
13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
14. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\
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