參數(shù)資料
型號: CY7C1387DV25-225BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
文件頁數(shù): 8/32頁
文件大小: 501K
代理商: CY7C1387DV25-225BZI
PRELIMINARY
CY7C1386DV25
CY7C1387DV25
Document #: 38-05548 Rev. **
Page 16 of 32
Identification Register Definitions
Instruction Field
CY7C1386DV25
CY7C1387DV25
Description
Revision Number (31:29)
000
Describes the version number.
Device Depth (28:24)
01011
Reserved for Internal Use
Device Width (23:18)
000110
Defines memory type and archi-
tecture
Cypress Device ID (17:12)
100101
010101
Defines width and density
Cypress JEDEC ID Code (11:1)
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence Indicator (0)
1
Indicates the presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size(x36)
Instruction
3
Bypass
1
ID
32
Boundary Scan Order (119-ball BGA package)
85
Boundary Scan Order (165-ball fBGA package)
89
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
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