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參數(shù)資料
| 型號(hào)： | CY7C1387DV25-225BZI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 CACHE SRAM, 2.8 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 32/32頁 |
| 文件大?。?/td> | 501K |
| 代理商： | CY7C1387DV25-225BZI |
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PRELIMINARY
CY7C1386DV25
CY7C1387DV25
Document #: 38-05548 Rev. **
Page 9 of 32
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
80
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
tZZI
ZZ Active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power Down
None
H
X
L
X
L
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
L
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
L
H
L
X
L-H
Tri-State
Deselect Cycle, Power Down
None
L
X
H
L
H
L
X
L-H
Tri-State
Sleep Mode, Power Down
None
X
H
X
Tri-State
READ Cycle, Begin Burst
External
L
H
L
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
X
H
L-H
Tri-State
WRITE Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
H
L
H
L
X
H
L-H
Tri-State
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
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