參數(shù)資料
型號: CY7C1387DV25-225BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
文件頁數(shù): 30/32頁
文件大小: 501K
代理商: CY7C1387DV25-225BZI
PRELIMINARY
CY7C1386DV25
CY7C1387DV25
Document #: 38-05548 Rev. **
Page 7 of 32
VDDQ
I/O Power Supply
Power supply for the I/O circuitry.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin has an internal pull-up.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be disconnected. This pin is
not available on TQFP packages.
TDI
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TMS
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
-
No Connects. Not internally connected to the die
Pin Definitions (continued)
Name
I/O
Description
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CY7C1387DV25-225BZC 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
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